WM8962B datasheet(149/295 Pages) WOLFSON

149 / 295 page

WM8962

Rev 4.3

149

CLOCKING AND SAMPLE RATES

The internal clocks for the WM8962 are all derived from a common internal clock source, SYSCLK.

This clock is the reference for the ADCs, DACs, DSP core functions, digital audio interface, Class D

switching amplifier, DC servo control and other internal functions.

SYSCLK can either be derived directly from MCLK, or may be generated from the Frequency Locked

Loop (FLL) or Phase Locked Loop (PLL). Many commonly-used audio sample rates can be derived

directly from typical MCLK frequencies; the FLL and PLL provide additional flexibility for a wide range

of reference frequencies. To avoid audible glitches, all clock configurations must be set up before

enabling playback. The FLL can be used to generate a free-running clock in the absence of an

external reference source; s

ee “Free-Running FLL Clock” for further details. See “Internal / External

Clock Generation

” for further details of the PLL and FLL circuits.

The WM8962 supports automatic clocking configuration. The programmable dividers associated with

the ADCs, DACs, DSP core functions, Class D switching and DC servo are configured automatically,

with values determined from the MCLK_RATE and SAMPLE_RATE fields. The user must also

configure the OPCLK (if required), the TOCLK (if required) and the digital audio interface.

ADC/DAC oversample rates of 64fs or 128fs are supported (based on a 48kHz sample rate).

A 256kHz clock, supporting a number of internal functions, is derived from SYSCLK.

The Class D switching amplifier and DC servo control circuits are clocked from SYSCLK.

A GPIO Clock, OPCLK, can be derived from SYSCLK and output on a GPIO pin to provide clocking to

other devices. This clock is enabled by OPCLK_ENA and controlled by OPCLK_DIV.

A slow clock, TOCLK, is used to set the timeout period for volume updates when zero-cross detect is

used. This clock is enabled by TOCLK_ENA and controlled by TOCLK_DIV. A de-bounce clock,

DBCLK, is used to control the de-bouncing of button/accessory detect GPIO inputs and selected

interrupt inputs. This clock is enabled automatically whenever GPIO or interrupt de-bouncing is

selected. The de-bounce clock frequency is controlled by DBCLK_DIV.

In master mode, BCLK is derived from DSPCLK via a programmable divider set by BCLK_DIV. In

master mode, the LRCLK is derived from BCLK via a programmable divider AIF_RATE.

In Slave mode, BCLK and LRCLK are inputs to the WM8962, allowing another digitial audio interface

to drive these pins. See the “BCLK and LRCLK Control” sub-section for specific operating constraints

in this configuration.

The control registers associated with Clocking and Sample Rates are shown in Table 98 to Table 103.

The overall clocking scheme for the WM8962 is illustrated in Figure 57.

WM8962B Datasheet(PDF) 149 Page - Wolfson Microelectronics plc