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WM8962B Datasheet(PDF) 145 Page - Wolfson Microelectronics plc

Part # WM8962B
Description  Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
PDF  295 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8962B Datasheet(HTML) 145 Page - Wolfson Microelectronics plc

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WM8962
Rev 4.3
145
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
9
AIFADC_TDM_
SLOT
0
ADCDAT TDM Slot Select
0 = ADCDAT data input on slot 0
1 = ADCDAT data input on slot 1
8
ADC_LRSWAP
0
Swap left/right ADC data on the interface
0 = Normal
1 = ADCDAT channels swapped
7
BCLK_INV
0
BCLK Invert
0 = BCLK not inverted
1 = BCLK inverted
5
DAC_LRSWAP
0
Swap left/right DAC data on the interface
0 = Normal
1 = DACDAT channels swapped
4
LRCLK_INV
0
Right, left and I2S modes
– LRCLK polarity
0 = normal LRCLK polarity
1 = invert LRCLK polarity
DSP Mode
– mode A/B select
0 = MSB is available on 2nd BCLK rising
edge after LRCLK rising edge (mode A)
1 = MSB is available on 1st BCLK rising
edge after LRCLK rising edge (mode B)
3:2
WL [1:0]
10
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Note -
see “Companding” for the selection of
8-bit mode.
1:0
FMT [1:0]
10
Digital Audio Interface Format
00 = Right justified
01 = Left justified
10 = I2S Format
11 = DSP Mode
Table 90 Digital Audio Interface Data Control
AUDIO INTERFACE TRI-STATE
Register bit AIF_TRI can be used to tri-state the audio interface pins as described in Table 91. All
digital audio interface pins will be tri-stated by this function, regardless of the state of other registers
which control these pin configurations.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
Additional
Control (2)
3
AIF_TRI
0
Audio Interface Tristate
0 = Audio interface pins operate normally
1 = ADCDAT is tri-stated; BCLK & LRCLK are
set as inputs
Table 91 Digital Audio Interface Tri-State Control
BCLK AND LRCLK CONTROL
The audio interface can be programmed to operate in master mode or slave mode using the MSTR
register bit.
In master mode, the BCLK and LRCLK signals are generated by the WM8962 when any of the ADCs
or DACs is enabled. In slave mode, the BCLK and LRCLK clock outputs are disabled by default to
allow another digital audio interface to drive these pins.
Refer to “Clocking and Sample Rates” for
specific operating constraints in this configuration.



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