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WM8962B Datasheet(PDF) 142 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 142 Page - Wolfson Microelectronics plc |
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142 / 295 page  WM8962 142 Rev 4.3 n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK DACDAT/ ADCDAT 1/2fs Figure 47 DSP Mode Audio Interface (mode B, LRCLK_INV=1, Master) n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK DACDAT/ ADCDAT 1 BCLK Falling edge can occur anywhere in this area 1 BCLK Figure 48 DSP Mode Audio Interface (mode A, LRCLK_INV=0, Slave) n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK DACDAT/ ADCDAT 1 BCLK 1 BCLK Falling edge can occur anywhere in this area Figure 49 DSP Mode Audio Interface (mode B, LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. WM8962 ADC data that is output on the Left Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the WM8962 will be treated as Left Channel data. This data may be routed to the Left/Right DACs as described in the “Digital Mixing” section. AUDIO DATA FORMATS (TDM MODE) TDM is supported in master and slave mode and is enabled by register bits AIFADC_TDM_MODE and AIFDAC_TDM_MODE. All audio interface data formats support time division multiplexing (TDM) for ADC and DAC data. Two time slots are available (Slot 0 and Slot 1), selected by register bits AIFADC_TDM_SLOT and AIFDAC_TDM_SLOT which control time slots for the ADC data and the DAC data. |
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