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WM8962B Datasheet(PDF) 146 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 146 Page - Wolfson Microelectronics plc |
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146 / 295 page ![]() WM8962 146 Rev 4.3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 (07h) Audio Interface 0 6 MSTR 0 Audio Interface Mode Select 0 = Slave mode 1 = Master mode R8 (08h) Clocking2 3:0 BCLK_DIV 0100 BCLK Rate 0000 = DSPCLK 0001 = Reserved 0010 = DSPCLK / 2 0011 = DSPCLK / 3 0100 = DSPCLK / 4 (default) 0101 = Reserved 0110 = DSPCLK / 6 0111 = DSPCLK / 8 1000 = Reserved 1001 = DSPCLK / 12 1010 = DSPCLK / 16 1011 = DSPCLK / 24 1100 = Reserved 1101 = DSPCLK / 32 1110 = DSPCLK / 32 1111 = DSPCLK / 32 R14 (0Eh) Audio Interface 2 10:0 AIF_RATE [10:0] 040h LRCLK Rate LRCLK clock output = BCLK / AIF_RATE Integer (LSB = 1) Valid from 4..2047 Default (040h) = 64 BCLKs per LRCLK Table 92 Digital Audio Interface Clock Control COMPANDING The WM8962 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 93. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 (09h) Audio Interface 1 4 DAC_COMP 0 DAC Companding Enable 0 = disabled 1 = enabled 3 DAC_COMPMODE 0 DAC Companding Type 0 = µ-law 1 = A-law 2 ADC_COMP 0 ADC Companding Enable 0 = disabled 1 = enabled 1 ADC_COMPMODE 0 ADC Companding Type 0 = µ-law 1 = A-law Table 93 Companding Control |
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