WM8962B datasheet(141/295 Pages) WOLFSON

141 / 295 page

WM8962

Rev 4.3

141

n-1

n-2

n-1

n-2

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Input Word Length (WL)

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

Figure 44 Left Justified Audio Interface (assuming n-bit word length)

In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

n-1

n-2

n-1

n-2

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Input Word Length (WL)

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

1 BCLK

Figure 45 I2S Justified Audio Interface (assuming n-bit word length)

In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge

of BCLK (selectable by LRCLK_INV) following a rising edge of LRCLK. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 46 and

Figure 47. In device slave mode, Figure 48 and Figure 49, it is possible to use any length of frame

pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK

period before the rising edge of the next frame pulse.

n-1

n-2

n-1

n-2

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Input Word Length (WL)

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

1 BCLK

1/2fs

Figure 46 DSP Mode Audio Interface (mode A, LRCLK_INV=0, Master)

WM8962B Datasheet(PDF) 141 Page - Wolfson Microelectronics plc

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