WM8962B datasheet(140/295 Pages) WOLFSON

140 / 295 page

WM8962

140

Rev 4.3

WM8962

Processor

WM8962 or

Similar

CODEC

ADCDAT

LRCLK

DACDAT

BCLK

ADCDAT

LRCLK

DACDAT

BCLK

Figure 42 TDM with Processor as Master

Note: The WM8962 is a 24-bit device. If the user operates the WM8962 in 32-bit mode then the 8

LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore

recommended to add a pull-down resistor, if necessary, to the DACDAT line and the ADCDAT line in

TDM mode.

BCLK FREQUENCY

The BCLK frequency is controlled relative to SYSCLK by the BCLK_DIV divider. Internal clock divide

and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable

and repeatable position relative to each other and relative to the data for a given combination of

DAC/ADC sample rate and BCLK_DIV settings.

BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also “Clocking and Sample

Rates

” section for more information.

AUDIO DATA FORMATS (NORMAL MODE)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

n-1

n-2

n-1

n-2

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Input Word Length (WL)

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

Figure 43 Right Justified Audio Interface (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

WM8962B Datasheet(PDF) 140 Page - Wolfson Microelectronics plc

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