WM8962B datasheet(151/295 Pages) WOLFSON

151 / 295 page

WM8962

Rev 4.3

151

Note that it is important that the GPIO5 input is held in a defined logic state (logi

c ‘0’ or logic ‘1’) during

start-up; it must not be left floating. If normal GPIO functionality is required on the GPIO5 pin, then the

CLKREG_OVD bit must be set

to ‘1’ in order to select normal read/write control of all the clocking

registers, and to permit GPIO functions.

The GPIO5 pin must be held in a defined logic state (logic ‘0’

or logic ‘1’) whenever the pin is configured as an input, including whenever CLKREG_OVD = 0

(default).

See “Internal / External Clock Generation” for more details of the FLL and PLL clock generators.

The SYSCLK signal is enabled by register bit SYSCLK_ENA. This bit should be set to 0 when

reconfiguring clock sources.

The following operating frequency limits are recommended when configuring SYSCLK. Failure to

observe these limits may result in degraded noise performance.



MCLK

 3MHz



If DAC_HP = 1 or ADC_HP = 1, then MCLK

 6MHz

The valid clocking ratios for DAC and/or ADC operation are identified in Table 96. See also Table 97

for details of the supported functions for each combination of Sample Rate and MCLK / fs ratio.

SAMPLE

RATE (kHz)

MCLK RATE (MCLK / fs ratio)

128

192

256

384

512

768

1024

1536

3072

6144

11.025

22.05

44.1

88.2

Table 96 MCLK / Sample Rate Availability

CODE

DAC/ADC

Configuration ADC Signal Path Enhancements

DAC Signal Path Enhancements

HPF,

LPF/HPF,

DF1 Filter,

3D Surround,

Dynamic Range

Control (DRC)

ReTune

Dynamic Range

Control (DRC)

5-band EQ

Virtual Surround

Sound (VSS),

ReTune

HD Bass,

DAC HPF

Mono DAC

Stereo DAC



Stereo CODEC



or Stereo DAC



Stereo CODEC



Stereo CODEC



Table 97 DAC/ADC and Audio Enhancements Availability

The supported MCLK frequency range is defined in the “Signal Timing Requirements”.

The MCLK / fs ratio is set using the MCLK_RATE register. See “Automatic Clocking Configuration” for

details of this register.

The MCLK and SYSCLK control register fields are defined in Table 98.

WM8962B Datasheet(PDF) 151 Page - Wolfson Microelectronics plc

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