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WM8962B Datasheet(PDF) 153 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 153 Page - Wolfson Microelectronics plc |
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153 / 295 page ![]() WM8962 Rev 4.3 153 The WM8962 is designed to support specific internal and external clocking configurations. Under default conditions, the GPIO5 pin has control over selected clocking registers, and normal read/write access to some registers is not supported. When the CLKREG_OVD register is set to 1, the affected clocking registers are controlled as normal via the Control Interface. The registers that are affected by CLKREG_OVD are noted in Table 99. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) ADC & DAC Control 2 0 DAC_HP 0 DAC Oversampling Ratio 0 = Low Power (typically 64 x fs) 1 = High Performance (typically 128 x fs) R8 (08h) Clocking2 11 CLKREG_OVD 0 Clock Configuration Override 0 = MCLK_SRC, OSC_ENA and CLKOUT5_SEL registers are controlled by the GPIO5 pin; PLL2_ENA, PLL3_ENA, CLKOUT2_DIV, CLKOUT5_DIV and CLKOUT3_SEL registers are locked to fixed values. 1 = Clocking registers are controlled as normal via Control Interface. This bit must be set to 1 to support GPIO functionality on GPIO5. R23 (17h) Additional Control (1) 5 ADC_HP 0 ADC Oversampling Ratio 0 = Low Power (typically 64 x fs) 1 = High Performance (typically 128 x fs) R27 (1Bh) Additional Control (3) 4 SAMPLE_RATE _INT_MODE 1 Selects the Integer or Fractional value of the SAMPLE_RATE register. 0 = 11.025k, 22.05k, 44.1k or 88.2kHz 1 = 8k, 12k, 16k, 24k, 32k, 48k or 96kHz 2:0 SAMPLE_RATE [2:0] 000 Selects the Sample Rate (fs) 000 = 44.1kHz, 48kHz 001 = 32kHz 010 = 22.05kHz, 24kHz 011 = 16kHz 100 = 11.025kHz, 12kHz 101 = 8kHz 110 = 88.2kHz, 96kHz 111 = Reserved R56 (38h) Clocking 4 4:1 MCLK_RATE [3:0] 0011 Selects the MCLK / fs ratio. (Note that the MCLK source is selected by MCLK_SRC.) 0000 = 64 0001 = 128 0010 = 192 0011 = 256 (default) 0100 = 384 0101 = 512 0110 = 768 0111 = 1024 1000 = Reserved 1001 = 1536 1010 = 3072 1011 = 6144 If ADC ReTune, DAC ReTune, DAC HPF, VSS or HD Bass is enabled, then MCLK_RATE must be 512 or higher. Table 99 Automatic Clocking Configuration Control |
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