WM8962B datasheet(156/295 Pages) WOLFSON

156 / 295 page

WM8962

156

Rev 4.3

OPCLK CONTROL

A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled by

This output of this clock is also dependent upon the GPIO register settings described in the General

Purpose Input/Output (GPIO)

” section.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Pwr Mgmt

(1)

OPCLK_ENA

GPIO Clock Output Enable

0 = Disabled

1 = Enabled

R30 (1Eh)

Clocking 3

12:10

OPCLK_DIV

[2:0]

000

GPIO Output Clock Divider

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

000 = SYSCLK / 16

Table 102 OPCLK Control

TOCLK, DBCLK CONTROL

A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input de-

bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA,

and its frequency is controlled by TOCLK_DIV.

A de-bounce clock, DBCLK, is used to control the de-bouncing of GPIO inputs and selected interrupt

inputs. This clock is enabled automatically whenever GPIO or interrupt de-bouncing is selected. The

de-bounce clock frequency is controlled by DBCLK_DIV.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R23 (17h)

Additional

Control(1)

TOCLK_ENA

TOCLK Enable

0 = Disabled

1 = Enabled

R30 (1Eh)

Clocking 3

15:13

DBCLK_DIV

[2:0]

000

DBCLK Rate Divider

(divides the 256kHz clock; nominal

frequency is quoted in brackets)

000 = f / 256 (1kHz)

001 = f / 2048 (125Hz)

010 = f / 4096 (62.5Hz)

011 = f / 8192 (31.2Hz)

100 = f / 16384 (15.6Hz)

101 = f / 32768 (7.8Hz)

110 = f / 64536 (3.9Hz)

111 = f / 131072 (1.95Hz)

9:7

TOCLK_DIV

[2:0]

000

TOCLK Rate Divider

(divides the 256kHz clock; nominal

frequency is quoted in brackets)

000 = f / 256 (1kHz)

001 = f / 512 (500Hz)

010 = f / 1024 (250Hz)

011 = f / 2048 (125Hz)

100 = f / 4096 (62.5Hz)

101 = f / 8192 (31.2Hz)

110 = f / 16384 (15.6Hz)

111 = f / 32768 (7.8Hz)

Table 103 TOCLK, DBCLK Control

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