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WM8962B Datasheet(PDF) 157 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 157 Page - Wolfson Microelectronics plc |
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157 / 295 page ![]() WM8962 Rev 4.3 157 BCLK AND LRCLK CONTROL In master mode, BCLK is derived from DSPCLK via a programmable division set by BCLK_DIV. In master mode, LRCLK is derived from BCLK via a programmable division set by AIF_RATE. See “Digital Audio Interface Control” for details of these fields. In Slave mode, BCLK/LRCLK should not be stopped whilst a DAC to Speaker playback path is active unless SYSCLK is also stopped. Failure to meet this requirement may result in a DC output at the speaker outputs, and possible speaker damage. In Slave mode, if BCLK/LRCLK may stop during DAC to Speaker playback then it is recommended to use a SYSCLK source that will also stop at the same time as BCLK/LRCLK. It is important to note that the FLL will continue to run even when its input reference is removed; if the FLL is selected as the SYSCLK source, then SYSCLK will not stop if BCLK/LRCLK is stopped. If SYSCLK is stopped whenever BCLK/LRCLK is stopped, or if the audio interface is operating in Master mode, then no specific action is required in relation to BCLK/LRCLK stopping. If BCLK/LRCLK may stop during DAC to Speaker playback, with SYSCLK still running, then it is recommended to disable the Speaker output (see “Output Signal Path”) or to disable the DAC to Speaker Mixer paths (see “Speaker Output Paths”) before stopping BCLK/LRCLK. If it is not possible to change the WM8962 settings before BCLK/LRCLK are stopped (ie. the BCLK/LRCLK inputs may stop unpredictably), then the DAC 2nd order HPF should be enabled in order to remove DC offsets in the output signal. See “DAC Signal Path Enhancements” for details of this feature. CONTROL INTERFACE CLOCKING Register map access is possible with or without a system clock (SYSCLK). The source for SYSCLK may be either the MCLK pin, FLL or PLL3, as described abov e in the “SYSCLK Control” section. When SYSCLK_ENA = 1, then an active clock source for SYSCLK must be present for control interface clocking. If the SYSCLK source is stopped, then SYSCLK_ENA must be set to 0 for control register access. |
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