WM8962B datasheet(158/295 Pages) WOLFSON

158 / 295 page

WM8962

158

Rev 4.3

INTERNAL / EXTERNAL CLOCK GENERATION

The WM8962 provides many features to generate clocks for internal and external use. The internal

SYSCLK is either generated from MCLK directly, or can be generated using the FLL or using PLL3.

The WM8962 Clock Generation options are illustrated in Figure 58.

24MHz

XTI/MCLK

XTO

Internal

Oscillator

PLL2

PLL3

MCLK source

GPIO2 output

GPIO3 output

PLL_CLK_SRC

OSC_ENA

PLL2_ENA

CLKOUT2_SEL

PLL3_ENA

CLKOUT3_SEL

MCLK_SRC

CLKOUT5_DIV

CLKOUT2_DIV

CLKOUT5_SEL

FLL_REFCLK_SRC

FLL_ENA

FLL_TO_PLL3

FLL

BCLK

CLKOUT3_DIV

PLL_SYSCLK_DIV

Divide by 1, 2 or 4

PLL2_OUTDIV

PLL3_OUTDIV

FLL_OUTDIV

CLKOUT5_OE

CLKOUT2_OE

CLKOUT3_OE

Figure 58 Clock Generation Block Diagram

The MCLK pin supports clock input from external source; this provides a reference for clocking the

WM8962 internal circuits via SYSCLK. The WM8962 also provides an internal oscillator circuit, using

an external crystal connected to the MCLK pin.

The output of the oscillator can be output directly on the CLKOUT2 or CLKOUT5 pins.

The WM8962 incorporates a Frequency Locked Loop (FLL). The input reference to the FLL is

selectable; it can be either the MCLK or BCLK pin directly, or else the internal oscillator. The FLL can

be used to generate SYSCLK; it can also be configured to provide an input reference to PLL3.

The WM8962 incorporates two Phase Locked Loop (PLL) circuits. The input reference to these PLLs

is selectable; it can either be the MCLK pin directly, or else the internal oscillator. The FLL output can

be selected as the input reference for PLL3 if required.

The PLLs can be used to generate a variety of clock signals from the available reference inputs.

These are configurable circuits which perform frequency multiplication and frequency division to suit

the application requirements. The PLLs are tolerant of jitter on the input reference and can therefore

be used to generate a stable output from a less stable input.

The signals generated by PLL2 and PLL3 can be output on the CLKOUT2 and CLKOUT3 pins

respectively. If any PLL output is not required, then the respective CLKOUT pin(s) can alternatively be

used for GPIO functions.

WM8962B Datasheet(PDF) 158 Page - Wolfson Microelectronics plc

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