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WM8962B Datasheet(PDF) 162 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 162 Page - Wolfson Microelectronics plc |
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162 / 295 page  WM8962 162 Rev 4.3 OSC_TRIM_XTI, OSC_TRIM_XTO DESCRIPTION OSC_TRIM_XTI, OSC_TRIM_XTO DESCRIPTION 00000 14.0pF 10000 22.0pF 00001 14.5pF 10001 22.5pF 00010 15.0pF 10010 23.0pF 00011 15.5pF 10011 23.5pF 00100 16.0pF 10100 24.0pF 00101 16.5pF 10101 24.5pF 00110 17.0pF 10110 25.0pF 00111 17.5pF 10111 25.5pF 01000 18.0pF 11000 25.5pF 01001 18.5pF 11001 25.5pF 01010 19.0pF 11010 25.5pF 01011 19.5pF 11011 25.5pF 01100 20.0pF 11100 25.5pF 01101 20.5pF 11101 25.5pF 01110 21.0pF 11110 25.5pF 01111 21.5pF 11111 25.5pF Table 107 Oscillator Trim Register Readback XTI_CAP_SEL, XTO_CAP_SEL DESCRIPTION XTI_CAP_SEL, XTO_CAP_SEL DESCRIPTION 0000 0.0pF 1000 -4.0pF 0001 +0.5pF 1001 -3.5pF 0010 +1.0pF 1010 -3.0pF 0011 +1.5pF 1011 -2.5pF 0100 +2.0pF 1100 -2.0pF 0101 +2.5pF 1101 -1.5pF 0110 +3.0pF 1110 -1.0pF 0111 +3.5pF 1111 -0.5pF Table 108 Oscillator Trim Adjustment Settings CLKOUT CONTROL The WM8962 provides three CLKOUT pins for FLL / PLL output. The selected function of each is determined by the CLKOUTn_SEL registers, where n represents the applicable pin. The available options are indicated in the register descriptions shown in Table 109. The CLKOUT3_SEL register is controlled automatically under certain circumstances, as noted in Table 109. The assoc iated control register, CLKREG_OVD, is defined in the “Automatic Clocking Configuration ” section, (see “Clocking and Sample Rates”). The CLKOUT5_SEL register is controlled automatically under certain circumstances, as described below. The associated control register, CLKREG_OVD, is defined in the “Automatic Clocking Configuration ” section, (see “Clocking and Sample Rates”). When a logic 0 is applied on the GPIO5 pin, the CLKOUT5_SEL register is set 1, selecting the FLL as the source. In this case, the CLKOUT5_SEL register is locked to prevent accidental writes to this register. The CLKOUT5_SEL register can be unlocked by setting the CLKREG_OVD bit. When a logic 1 is applied on the GPIO5 pin, the CLKOUT5_SEL register defaults to 0, selecting the Oscillator as the source. In this case, the default (0) is selected on the rising edge of GPIO5; other settings can then be selected by writing to the CLKOUT5_SEL register as normal. Note that, if GPIO functionality is required on the GPIO5 pin, then the CLKREG_OVD bit must be set to ‘1’ in order to select normal read/write control of the CLKOUT5_SEL register. |
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