WM8962B datasheet(152/295 Pages) WOLFSON

152 / 295 page

WM8962

152

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Clocking1

2:1

SYSCLK_DIV

SYSCLK Divider

00 = MCLK

01 = MCLK / 2

10 = MCLK / 4

11 = Reserved

This field is for read-back only; it is set

automatically and cannot be adjusted.

Note that the division is applied to the

selected MCLK source, including FLL /

PLL when applicable.

R8 (08h)

Clocking2

10:9

MCLK_SRC

MCLK source select

00 = MCLK pin

01 = FLL output

10 = PLL3 output

11 = Reserved

If CLKREG_OVD = 0, then MCLK_SRC

is controlled by the GPIO5 pin.

If CLKREG_OVD = 0 and GPIO5 = 1,

then MCLK_SRC = 01 (FLL) and

MCLK_SRC cannot be changed by the

Control Interface.

If CLKREG_OVD = 0 and GPIO5 = 0,

then MCLK_SRC = 00 (MCLK) by

default, but the value can be changed

via the Control Interface.

If CLKREG_OVD = 1 then MCLK_SRC

= 00 (MCLK) by default, but the value

can be changed via the Control

Interface.

SYSCLK_ENA

SYSCLK enable

0 = Disabled

1 = Enabled

R125 (7Dh)

Analogue

Clocking2

4:3

PLL_SYSCLK_

DIV

PLL3 to SYSCLK divider

00 = PLL3 / 1

01 = PLL3 / 2

10 = PLL3 / 4

11 = Reserved

Table 98 MCLK and SYSCLK Control

AUTOMATIC CLOCKING CONFIGURATION

The WM8962 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The

Automatic Clocking Configuration mode simplifies the configuration of the clock dividers in the

WM8962 by deriving most of the necessary parameters from a minimum number of user registers.

In Automatic mode, the SAMPLE_RATE field selects the sample rate, fs, of the ADC and DAC. The

SAMPLE_RATE_INT_MODE bit should be set according to the selected SAMPLE_RATE, as

described in Table 99. Note that, in Automatic mode, the same sample rate always applies to the ADC

and DAC.

In Automatic mode, the MCLK_RATE field must be set according to the ratio of MCLK to fs. (Note that

the MCLK source is selected by MCLK_SRC - see Table 98.)

Selectable modes of ADC / DAC operation are available using the ADC_HP and DAC_HP register

bits. The automatic clocking configuration uses these bits to determine the applicable clock divider

settings.

WM8962B Datasheet(PDF) 152 Page - Wolfson Microelectronics plc

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