WM8962B datasheet(180/295 Pages) WOLFSON

180 / 295 page

WM8962

180

Rev 4.3

Interrupt Status fields remain valid, even when masked, but the masked bits will not cause the

Interrupt Output to be asserted.

The Interrupt Output represents the logical ‘OR’ of all the unmasked IRQ inputs, as illustrated in

Figure 62. The bits within the Interrupt Status register (R560 and R561) are latching fields and, once

they are set, they are not reset until

a ‘1’ is written to the respective register bit in the Interrupt Status

registers. The Interrupt (IRQ) output is not reset until each of the unmasked IRQ inputs has been

reset. Note that, if the condition that caused the IRQ input to be asserted is still valid, then the

Interrupt Output will remain set even after the Status register has been written to.

The PLLn_LOCK_EINT, FLL_LOCK_EINT and TEMP_SHUT_EINT inputs to the Interrupt Controller

can be de-bounced to avoid false detections. The timeout clock (TOCLK) is required for this function.

The de-bounce is enabled on these inputs using the bits in Register R584. The de-bounce clock is

enabled automatically whenever interrupt de-bouncing is selected. The de-bounce clock frequency is

controlled by DBCLK_DIV as described in

“Clocking and Sample Rates”.

By default, the Interrupt Output is Active High. The polarity can be inverted using IRQ_POL.

The WM8962 Interrupt Controller circuit is illustrated in Figure 54. The associated control fields are

described in Table 120.

IM_ALC_SAT_EINT

IM_ALC_PKOVR_EINT

IM_ALC_NGATE_EINT

INTERRUPT

(IRQ)

IM_WSEQ_DONE_EINT

IM_DRC_ACTDET_EINT

IM_PLL3_LOCK_EINT

ALC_NGATE_IRQ

WSEQ_IRQ

DRC_ACTDET_IRQ

PLL3_LOCK_IRQ

IRQ_POL

IM_FIFOS_ERR_EINT

IM_ALC_LOCK_EINT

IM_ALC_THRESH_EINT

IM_PLL2_LOCK_EINT

IM_FLL_LOCK_EINT

IM_TEMP_SHUT_EINT

FIFOS_ERR_EINT

ALC_LOCK_EINT

ALC_THRESH_EINT

ALC_SAT_EINT

ALC_PKOVR_EINT

ALC_NGATE_EINT

WSEQ_DONE_EINT

DRC_ACTDET_EINT

PLL3_LOCK_EINT

PLL2_LOCK_EINT

FLL_LOCK_EINT

TEMP_SHUT_EINT

Status

Latches

Read only;

cleared on

Write ‘1’

PLL2_LOCK_IRQ

FLL_LOCK_IRQ

TEMP_SHUT_IRQ

FIFOS_ERR_IRQ

ALC_LOCK_IRQ

ALC_THRESH_IRQ

ALC_SAT_IRQ

ALC_PKOVR_IRQ

IM_GP6_EINT

IM_GP5_EINT

GP6_EINT

GP5_EINT

GP6_IRQ

GP5_IRQ

IM_MICSCD_EINT

MICSCD_EINT

MICSCD_IRQ

IM_MICD_EINT

MICD_EINT

MICD_IRQ

Figure 62 Interrupt Controller

WM8962B Datasheet(PDF) 180 Page - Wolfson Microelectronics plc

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