WM8962B datasheet(185/295 Pages) WOLFSON

185 / 295 page

WM8962

Rev 4.3

185

SDOUT function on GPIO2 and GPIO3 is not configurable using SPI_CFG; on these pins, SDOUT is

a CMOS output at all times.

The Control Interface configuration bits are described in Table 122.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R94 (005Eh)

Control Interface

SPI_CONTRD

Enable continuous read mode in SPI (3-

wire/4-wire) modes

0 = Disabled

1 = Enabled

SPI_4WIRE

SPI control mode select

0 = 3-wire using bidirectional SDA

1 = 4-wire using SDOUT

SPI_CFG

SDA/SDOUT pin configuration

In 3-wire mode (SPI_4WIRE=0):

0 = SDA output is CMOS

1 = SDA output is Open Drain

In 4-wire mode (SPI_4WIRE=1):

0 = SDOUT output is CMOS

1 = SD

OUT output is Wired ‘OR’.

Note that only GPIO5 can be configured

as Wired ‘OR’. This bit has no effect on

GPIO2 or GPIO3.

R252 (00FFh)

AUTO_INC

Enables address auto-increment

(applies to 2-wire I2C mode only)

0 = Disabled

1 = Enabled

Table 122 Control Interface Configuration

2-WIRE (I2C) CONTROL MODE

In 2-wire (I2C) mode, the WM8962 is a slave device on the control interface; SCLK is a clock input,

while SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters)

on the same interface, the WM8962 transmits logic 1 by tri-stating the SDA pin, rather than pulling it

high. An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be

recognised by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 8-bit device ID (this is not the same as the address of each register in the WM8962). The

WM8962 device ID is 0011_0100 (34h). The LSB of the device ID is the Read/Write bit; this bit is set

to logic 1 for “Read” and logic 0 for “Write”.

Important - in addition to the I2C address noted above (34h), the WM8962 also incorporates test

functionality via I2C addresses 94h and D2h, and may respond to I2C operations at these addresses.

It is a requirement that no other device on the same I2C bus makes use of address 94h or D2h.

The WM8962 operates as a slave device only. The controller indicates the start of data transfer with a

high to low transition on SDA while SCLK remains high. This indicates that a device ID, register

address and data will follow. The WM8962 responds to the start condition and shifts in the next eight

bits on SDA (8-bit device ID, including Read/Write bit, MSB first). If the device ID received matches

the device ID of the WM8962, then the WM8962 responds by pulling SDA low on the next clock pulse

(ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only mode, the

WM8962 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8962, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCKL remains high. After receiving a complete address and data sequence the WM8962 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns

to the idle condition.

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