DP8420V datasheet(34/60 Pages) NSC

Part #	DP8420V

Description	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

PDF	60 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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34 / 60 page

70 RAS and CAS Configuration Modes (Continued)

TLF11109 – 45

FIGURE 28a DRAM Array Setup for 4 Banks Using Address Pipelining (C6 C5 C4 e 1 1 1

or C6 C5 C4 e 0 1 0 (Also Allowing Error Scrubbing) during Programming)

TLF11109 – 46

FIGURE 28b DRAM Array Setup for Address Pipelining with 2 Banks (C6 C5 C4 e 1 0 1

or C6 C5 C4 e 0 0 1 (Also Allowing Error Scrubbing) during Programming)

74 ERROR SCRUBBING

In error scrubbing during refresh the user selects one two

or four RAS and CAS outputs per bank When performing

error detection and correction memory is always accessed

as words Since the CAS signals are not used to select

individual bytes the ECAS inputs can be tied low as shown

Figures 29a and 29b

TLF11109 – 47

FIGURE 29a DRAM Array Setup for 4 Banks Using Error Scrubbing (C6 C5 C4 e 0 1 0 during Programming)

TLF11109 – 48

FIGURE 29b DRAM Array Setup for Error Scrubbing with 2 Banks (C6 C5 C4 e 0 0 1 during Programming)

DP8420V Datasheet(PDF) 34 Page - National Semiconductor (TI)