DP8420V datasheet(38/60 Pages) NSC

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100 Dual Accessing (DP8422V DP84T22) (Continued)

102 PORT B WAIT STATE SUPPORT

Advanced transfer acknowledge for Port B ATACKB is

used for wait state support for Port B This output will be

asserted when RAS for the Port B access is asserted as

shown in

Figures 33a and 33b Once asserted this output

will stay asserted until AREQB is negated With external

logic ATACKB can be made to interface to any CPU’s wait

input as shown in

Figure 33c

103 COMMON PORT A AND PORT B DUAL PORT

FUNCTIONS

An input LOCK and an output GRANTB add additional

functionality to the dual port arbitration logic LOCK allows

Port A or Port B to lock out the other port from the DRAM

When a Port is locked out of the DRAM wait states will be

inserted into its access cycle until it is allowed to access

memory GRANTB is used to multiplex the input control sig-

nals and addresses to the DP8422V DP84T22

1031 GRANTB Output

The output GRANTB determines which port has current ac-

cess to the DRAM array GRANTB asserted signifies Port B

has access GRANTB negated signifies Port A has access

to the DRAM array

TLF11109 – 54

FIGURE 33a Non-Delayed Port B Access

TLF11109 – 55

FIGURE 33b Delayed Port B Access

TLF11109 – 56

A Extend ATACK to

Clock) after RAS goes low

TLF11109 – 57

B Extend ATACK to 1T after RAS goes low

TLF11109 – 58

C Synchronize ATACKB to CPU B Clock This is useful if CPU B runs asynchronous to the DP8422V DP84T22

FIGURE 33c Modifying Wait Logic for Port B

DP8420V Datasheet(PDF) 38 Page - National Semiconductor (TI)