DP8420V datasheet(35/60 Pages) NSC

35 / 60 page

70 RAS and CAS Configuration Modes (Continued)

75 PAGEBURST MODE

In a static column page or burst mode system the least

significant bits must be tied to the column address in order

to ensure that the pageburst accesses are to sequential

memory addresses as shown in

Figure 30

In a nibble

mode system the least significant bits must be tied to the

highest column and row address bits in order to ensure that

sequential address bits are the ‘‘nibble’’ bits for nibble mode

accesses

(Figure 30) The ECAS inputs may then be tog-

gled with the DP8420V21V22V’s DP84T22’s address

latches in fall-through mode while AREQ is asserted The

ECAS inputs can also be used to select individual bytes

When using nibble mode DRAMS the third and fourth ad-

dress bits can be tied to the bank select inputs to perform

memory interleaving In page or static column modes the

two address bits after the page size can be tied to the bank

select inputs to select a new bank if the page size is ex-

ceeded

TLF11109 – 49

See table below for row column

bank address bit map A0 A1 are used for byte addressing in this example

Addresses

Nibble Mode

Page ModeStatic Column Mode Page Size

256 BitsPage

512 BitsPage

1024 BitsPage

2048 BitsPage

Column

C9R9 e A2A3

C0 – 7 e A2–9

C0–8 e A2–10

C0–9 e A2–11

C0–10 e A2–12

Address

C0 – 8 e X

C8–10 e X

C910 e X

C10 e X

Row

Address

A10

A11

A12

A13

A11

A12

A13

A14

Assume that the least significant address bits are used for byte addressing Given a 32-bit system A0A1 would be

used for byte addressing

X e DON’T CARE the user can do as he pleases

Nibble mode values for R and C assume a system using 1 Mbit DRAMs

FIGURE 30 Page Static Column Nibble Mode System

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