LM3528 datasheet(4/34 Pages) TI1

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LM3528

SNVS513B – AUGUST 2008 – REVISED MAY 2013

www.ti.com

Electrical Characteristics (continued)

Specifications in standard type face are for TA = 25°C and those in boldface type apply over the Operating Temperature

Range of TA = −40°C to +85°C. Unless otherwise specified VIN = 3.6V, VIO = 1.8V, VRESET/GPIO = VIN, VSUB/FB = VMAIN = 0.5V,

SET

= 12.0k

Ω, OLED = ‘0’, ENM = ENS = ‘1’, BSUB = BMAIN = Full Scale.

(1) (2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

ILED-MATCH

IMAIN to ISUB/FB Current

UNI = ‘1’,

0.15

Matching

2.5V < VIN < 5.5V

(3)

VSET

SET Pin Voltage

3.0V < VIN < 5V

1.244

ILED/ISET

ILED Current to ISET Current

192

Ratio

VREG_CS

Regulated Current Sink

500

Headroom Voltage

VREG_OLED

VSUB/FB Regulation Voltage in 2.5V < VIN < 5.5V, OLED =

1.170

1.21

1.237

OLED Mode

‘1’

VHR

Current Sink Minimum

ILED = 95% of nominal

300

Headroom Voltage

RDSON

NMOS Switch On Resistance ISW = 100mA

0.43

Ω

ICL

NMOS Switch Current Limit

2.5V < VIN < 5.5V

645

770

900

VOVP

Output Over-Voltage

ON Threshold,

20.6

Protection

2.5V < VIN < 5.5V

OFF Threshold,

19.25

20.6

21.5

2.7V < VIN < 5.5V

fSW

Switching Frequency

1.0

1.27

1.4

MHz

DMAX

Maximum Duty Cycle

DMIN

Minimum Duty Cycle

Quiescent Current, Device

VMAIN and VSUB/FB >

Not Switching

VREG_CS,

350

390

BSUB = BMAIN = 0x00, 2.5V

< VIN < 5.5V

µA

VSUB/FB > VREG_OLED,

OLED=’1’, ENM=ENS=’0’,

250

260

RSET Open,

2.5V < VIN < 5.5V

ISHDN

Shutdown Current

ENM = ENS = OLED = '0',

1.8

µA

2.5V < VIN < 5.5V

HWEN/PGEN/GPIO, GPIO1 Pin Voltage Specifications

VIL

Input Logic Low

2.5V < VIN <5.5V, MODE bit

0.5

= 0

VIH

Input Logic High

2.5V < VIN < 5.5V, MODE bit

1.1

= 0

VOL

Output Logic Low

ILOAD=3mA, MODE bit = 1

400

I2C Compatible Voltage Specifications (SCL, SDA, VIO)

VIO

Serial Bus Voltage Level

2.5V < VIN < 5.5V

(4)

1.7

VIN

VIL

Input Logic Low

2.5V < VIN < 5.5V

0.36×VIO

VIH

Input Logic High

2.5V < VIN < 5.5V

0.7×VIO

VOL

Output Logic Low

ILOAD = 3mA

400

I2C Compatible Timing Specifications (SCL, SDA, VIO, see Figure 4) (5)(4)

SCL Clock Period

2.5

µs

Data In Setup Time to SCL

100

High

Data Out Stable After SCL

Low

(3)

The matching specification between MAIN and SUB is calculated as 100 × ((IMAIN or ISUB) - IAVE) / IAVE. This simplifies out to be 100 ×

(IMAIN - ISUB)/(IMAIN + ISUB).

(4)

SCL and SDA signals are referenced to VIO and GND for minimum VIO voltage testing. VIO limits indicate the minimum voltage at VIO

at which the part is operational.

(5)

SCL and SDA must be glitch-free in order for proper brightness control to be realized.

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