PCI4510 datasheet(43/220 Pages) TI

43 / 220 page

2−25

Table 2−18. Power Supply Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

RGVF

I/O

DESCRIPTION

ANALOGGND

U11

R12

R13

N12

U14

U16

−

Analog circuit ground terminals.

ANALOGVCC

R11

U13

U14

R13

R14

V17

−

Analog circuit power terminals. A parallel combination of high frequency decoupling

capacitors near each terminal is suggested, such as 0.1

µF and 0.001 µF. Lower frequency

10-

µF filtering capacitors are also recommended. These supply terminals are separated

from PLLVCC and PLLGND internal to the device to provide noise isolation. They must be

tied at a low-impedance point on the circuit board.

PLLGND

108

N14

P14

−

PLL circuit ground terminals. This terminal must be tied to the low-impedance circuit board

ground plane.

PLLVCC

107

P15

V19

−

PLL circuit power terminals. A parallel combination of high frequency decoupling capacitors

near the terminal is suggested, such as 0.1

µF and 0.001 µF. Lower frequency 10-µF

filtering capacitors are also recommended. This supply terminal is separated from AVDx

internal to the device to provide noise isolation. It must be tied at a low-impedance point on

the circuit board.

Table 2−19. Smart Card and Memory Card Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

RGVF

I/O

DESCRIPTION

MC_RSVD

113, 115, 116,

117, 118, 119,

120, 121, 122

N15, M14, N17,

N18, N19, M15,

M17, M18, M19

H07, G05, G03,

H03, G02, J06,

H05, F03, G01

−

Memory card terminals. Reserved for future use. These ter-

minals must be left unconnected.

SC_RSVD

196, 197, 198,

199, 200, 201,

202

A06, B06, B07,

C06, C07, E07,

F07

J01, J02, J03,

J05, J07, K01,

K02

−

Smart card terminals. Reserved for future use. These termi-

nals must be left unconnected.

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