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PCI4510 Datasheet(PDF) 77 Page - Texas Instruments |
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PCI4510 Datasheet(HTML) 77 Page - Texas Instruments |
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77 / 220 page  4−5 4.6 Class Code and Revision ID Registers The class code and revision ID register recognizes the PCI4510 device as a bridge device (06h) and CardBus bridge device (07h) with a (00h) programming interface. Furthermore, the TI chip revision (02h) is indicated in the least significant byte. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Class code Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code Revision ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Register: Class code and revision ID Offset: 08h (Function 0) Type: Read-only Default: 0607 0002h 4.7 Cache Line Size Register The cache line size register is programmed by host software to indicate the system cache line size. Bit 7 6 5 4 3 2 1 0 Name Cache line size Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Cache line size Offset: 0Ch (Function 0) Type: Read/Write Default: 00h 4.8 Latency Timer Register The latency timer register specifies the latency timer for the PCI4510 device, in units of PCI clock cycles. When the PCI4510 device is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI4510 transaction has terminated, then the PCI4510 device terminates the transaction when its GNT is deasserted. Bit 7 6 5 4 3 2 1 0 Name Latency timer Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Latency timer Offset: 0Dh Type: Read/Write Default: 00h |
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