LM87 datasheet(33/43 Pages) TI1

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LM87

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SNAS034J – APRIL 2000 – REVISED MARCH 2013

VID0-3/Fan Divisor Register—Address 47h

Power on default – <7:4> is 0101, and <3:0>is mapped to VID <3:0>

Bit

Name

Read/Write

Description

0-3 VID <3:0>

Read Only

The VID <3:0> inputs from the Pentium/PRO power supplies that indicate the operating voltage

(e.g. 1.5 V to 2.9 V).

4-5 FAN1 RPM Control Read/Write

FAN1 Speed Control.

<5:4> = 00 - divide by 1;

<5:4> = 01 - divide by 2;

<5:4> = 10 - divide by 4;

<5:4> = 11 - divide by 8.

6-7 FAN2 RPM Control Read/Write

FAN2 Speed Control.

<7:6> = 00 - divide by 1;

<7:6> = 01 - divide by 2;

<7:6> = 10 - divide by 4;

<7:6> = 11 - divide by 8.

VID4 Register—Address 49h

Power on default – <7:1> = 100 000, <0> = VID4.

Bit

Name

Read/Write

Description

VID4

Read Only

Bit 4 of VID data from the CPU or power supply that indicates the operating voltage (e.g. 1.5

V to 2.9 V).

1-7 Reserved

Read/Write

Configuration Register 2—Address 4Ah

Power on default – <7:0> = 0000 0000 binary

Bit

Name

Read/Write

Description

Thermal INT# Mask

Read/Write

When this bit is set to 1, thermal error events will not affect the INT# interrupt output.

THERM# outputs will still function normally.

Local Temp. Register

Read/Write

When set to 1, this bit locks in the value set in the Internal Temp. high limit register at 0x13h.

Write Once Bit

Once

The value cannot be changed until a power on reset is performed, or the chip is re-Initialized

by writing a 1 to Bit 7 of Configuration Register 1 (Register 40h).

Remote Temp.

Read/Write

When set to 1, this bit locks in the value set in the External Temp. high limit register at

Once

0x14h. The value cannot be changed until a power on reset is performed, or the chip is re-

Bit

Initialized by writing a 1 to Bit 7 of Configuration Register 1 (Register 40h).

THERM# Interrupt

Read/Write

When set to 0, the THERM# output functions in Default mode. When set to 1, the THERM#

Mode

output functions in ACPI mode.

4-5

Reserved

IRQ3 Enable

Read/Write

When set to 1, VID3/IRQ3 is enabled as an active high interrupt input (if the IRQEN bit is set

in bit 7 of the Channel Mode Register).

IRQ4 Enable

Read/Write

When set to 1, VID4/IRQ4 is enabled as an active high interrupt input (if the IRQEN bit is set

in bit 7 of the Channel Mode Register).

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