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UPD720122 Datasheet(PDF) 24 Page - NEC

Part # UPD720122
Description  MOS Integrated Circuit
PDF  82 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD720122 Datasheet(HTML) 24 Page - NEC

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Data Sheet S16685EJ2V0DS
24
µPD720122
(4) CPU bus DMA transfer
(a) CPU bus DMA single mode read transfer timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
T21
DMA request acknowledge setup time (RDB
↓)
0
∞
ns
T22
DMA request off time (EP1_DACKB
↓)
−
54
ns
T23
DMA single mode read transfer cycle time
91
∞
ns
T24
Read command width
57
∞
ns
T25
Read command inactive time
34
∞
ns
T26
Read data delay time (RDB
↓)
−
57
ns
T27
Buffer direction change time (RDB
↓)
−
14
ns
T28
Read data hold time (RDB
↑)
4
−
ns
T29
EP1_TCB setup time (RDB
↓)
0
Note
ns
T30
EP1_TCB hold time (RDB
↓)
17
∞
ns
T31
EP1_STOPB delay time (RDB
↓)
−
15
ns
T32
EP1_STOPB OFF delay time (RDB
↑)
3
−
ns
T33
DMA request acknowledge hold time (RDB
↑)
0
∞
ns
T34
Undefined
−−
ns
Note
Can be input after previous RDB
↑.
Remark
It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP1_DRQB
EP1_TCB
D15 to D0
RDB
EP1_DACKB
t22
t33
t24
t25
t26
t28
High level
EP1_STOPB
High level
EP1_STOPB is not asserted in the
case of a full packet.
N cycle
N
−−−− 1 cycle
1 cycle
t21
t23
t27
t31
t32



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