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UPD720122 Datasheet(PDF) 40 Page - NEC |
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UPD720122 Datasheet(HTML) 40 Page - NEC |
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40 / 82 page  Data Sheet S16685EJ2V0DS 40 µPD720122 (2) CPU bus write operation Symbol Parameter Min. Typ. Max. Unit TB13 Write cycle time 58 ∞ ns TB14 Address setup time (ALE ↓) 17 ∞ ns TB15 Chip select setup time (ALE ↓) 17 ∞ ns TB16 Write command delay time (ALE ↓) 7 ∞ ns TB17 Input data setup time (WRB ↑) 10 ∞ ns TB18 Input data hold time (WRB ↑) 0 ∞ ns TB19 Write command width 34 ∞ ns TB20 Chip select hold time (WRB ↑) 0 ∞ ns TB21 Chip select setup time (WRB ↓) 5 ∞ ns Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). CPU bus write timing WRB AD7 to AD0 Note D15 to D8 CSB ADDRESS VALID tb18 tb19 ALE DATA VALID tb2 tb16 tb20 ADDRESS VALID tb13 tb17 tb10 tb21 tb15 tb9 Note D7 to D0 for Function 2 |
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