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UPD720122 Datasheet(PDF) 70 Page - NEC |
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UPD720122 Datasheet(HTML) 70 Page - NEC |
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70 / 82 page  Data Sheet S16685EJ2V0DS 70 µPD720122 Figure 2-11. USB Receiver Jitter Tolerance for Full-Speed Differential data lines Paired transitions N * TPERIOD + TxJR2 TPERIOD Consecutive transitions N * TPERIOD + TxJR1 TxJR TxJR1 TxJR2 (3) USB connection sequence on USB1.1 bus The PHY core implemented on the µPD720122 automatically determines the Up port. Check the SP_MODE bit (SP_MODE) of the Int Status 2 register after an EPC2_STG bus reset interrupt has occurred to determine whether the USB is connected to FS or HS. Figure 2-12. USB Connection Sequence on USB 1.1 Bus tHDS tSCA tCKO tCKI tSCS tFCA tDRS Chirp K device out Reversion to full-speed mode FS J FS J Pull-up is active. T0 High USB bus USBRST SPMODE |
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