THS3095DDA datasheet(22/31 Pages) TI

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500

1000

1500

2000

2500

100 k

1 M

10 M

100 M

1 G

−

1.21 k

Ω 1.21 kΩ

Ω VO

f − Frequency − Hz

VS = ±15 V and ±5 V

POWER-DOWN REFERENCE PIN

PRINTED-CIRCUIT BOARD LAYOUT

THS3091

THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

PERFORMANCE

Achieving

optimum

performance

with

high-frequency amplifier, like the THS3091/5, re-

quires careful attention to board layout parasitic and

external component types.

Recommendations that optimize performance include:

•

Minimize parasitic capacitance to any ac ground

for all of the signal I/O pins. Parasitic capacitance

on the output and input pins can cause instability.

To reduce unwanted capacitance, a window

around the signal I/O pins should be opened in all

of the ground and power planes around those

pins. Otherwise, ground and power planes should

be unbroken elsewhere on the board.

Figure 70. Power-down Output Impedance vs

Frequency

•

Minimize the distance (< 0.25 in.) from the power

supply pins to high-frequency 0.1-µF and 100-pF

decoupling capacitors. At the device pins, the

As with most current feedback amplifiers, the internal

ground and power plane layout should not be in

architecture places some limitations on the system

close proximity to the signal I/O pins. Avoid

when in power-down mode. Most notably is the fact

narrow power and ground traces to minimize

that the amplifier actually turns ON if there is a

±0.7 V

inductance between the pins and the decoupling

or greater difference between the two input nodes

capacitors. The power supply connections should

(V+ and V-) of the amplifier. If this difference exceeds

always be decoupled with these capacitors.

±0.7 V, the output of the amplifier creates an output

Larger (6.8 µF or more) tantalum decoupling

voltage

equal

approximately

capacitors, effective at lower frequency, should

[(V+ - V-) -0.7 V]

×Gain. This also implies that if a

also be used on the main supply pins. These may

voltage is applied to the output while in power-down

be placed somewhat farther from the device and

mode,

the

V-

node

voltage

equal

may be shared among several devices in the

VO(applied)× RG/(RF + RG). For low gain configurations

same area of the PC board.

and a large applied voltage at the output, the

•

Careful selection and placement of external

amplifier

may

actually

turn

due

the

components

preserve

the

high-frequency

aforementioned behavior.

performance of the THS3091/5. Resistors should

The time delays associated with turning the device on

be a low reactance type. Surface-mount resistors

and off are specified as the time it takes for the

work best and allow a tighter overall layout.

amplifier to reach either 10% or 90% of the final

Again, keep their leads and PC board trace

output voltage. The time delays are in the order of

length as short as possible. Never use wirebound

microseconds because the amplifier moves in and out

type resistors in a high-frequency application.

of the linear mode of operation in these transitions.

Because the output pin and inverting input pins

are the most sensitive to parasitic capacitance,

always position the feedback and series output

OPERATION

resistors, if any, as close as possible to the

inverting input pins and output pins. Other net-

In addition to the power-down pin, the THS3095

work components, such as input termination re-

features a reference pin (REF) which allows the user

sistors, should be placed close to the gain-setting

to control the enable or disable power-down voltage

resistors. Even with a low parasitic capacitance

levels applied to the PD pin. In most split-supply

shunting

the

external

resistors,

applications, the reference pin is connected to

excessively high resistor values can create sig-

ground. In either case, the user needs to be aware of

nificant time constants that can degrade perform-

voltage-level thresholds that apply to the power-down

ance. Good axial metal-film or surface-mount

pin. The usable range at the REF pin is from VS- to

resistors have approximately 0.2 pF in shunt with

(VS+ - 4 V).

the resistor. For resistor values > 2 k

Ω, this

parasitic capacitance can add a pole and/or a

zero that can effect circuit operation. Keep re-

TECHNIQUES FOR OPTIMAL

sistor values as low as possible, consistent with

load-driving considerations.

•

Connections to other wideband devices on the

board may be made with short direct traces or

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