THS4271 datasheet(29/38 Pages) TI

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THS4271

THS4275

SLOS397E − JULY 2002 − REVISED JANUARY 2004

www.ti.com

In order to achieve the maximum performance of the

device, PCB layout is very critical. Texas Instruments has

developed an EVM for the evaluation of the THS4271 in a

gain of 1. The EVM is shown in Figure 101 through

Figure 104. This EVM is designed to minimize peaking in

the unity gain configuration.

Minimizing the inductance in the feedback path is critical

for reducing the peaking of the frequency response in unity

gain. The recommended maximum inductance allowed in

the feedback path is 4 nH. This can be calculated by using

Equation 8.

L(nH)

+ K ln 2

) T )

0.223 W ) T

) 0.5

where:

W = Width of trace in inches.

= Length of the trace in inches

T = Thickness of the trace in inches.

K = 5.08 for dimensions in inches, and K = 2 for dimensions

in cm.

Figure 95. THS4271/THS4275 EVM Circuit

Configuration

Vin+

Vs+

Power Down Ref

Vs+

Vs −

Power Down

Vout

Vs −

Vin−

TP1

VS−

VS+

FB2

FB1

VS−

GND

VS+

Figure 96. THS4271/THS4275 EVM Board

Layout (Top Layer)

Figure 97. THS4271/THS4275 EVM Board

Layout (Second Layer, Ground)

(8)

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