A3924 datasheet(19/55 Pages) ALLEGRO

19 / 55 page

Automotive, Full-Bridge MOSFET Driver

A3924

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

If the dead-time is to be generated externally (for example, by

the PWM output of a microcontroller), then entering a value of

zero in DT[5:0] will disable the dead timer, and there will be no

minimum dead time generated by the A3924. However, the logic

that prevents permanent cross-conduction will still be active.

The internally generated dead time will only be present if the on

command for one MOSFET occurs within one dead time after the

off command for its complementary partner. In the case where

one side of a phase drive is permanently off (for example, when

using diode rectification with slow decay), then the dead time

will not occur. In this case, the gate drive will turn on within the

specified propagation delay after the corresponding phase input

goes high. (see Figure 3)

Logic Control Inputs

Four logic level digital inputs provide direct control for the gate

drives, one for each drive. These TTL threshold logic inputs can

be driven from 3.3 or 5 V logic, and all have a typical hysteresis

of 500 mV to improve noise performance. Each input can be

shorted to the VBB supply, up to the absolute maximum supply

voltage, without damage to the input.

Input HA is active-high and controls the high-side drive for phase

A. LAn is active-low and controls the low-side drive for phase

A. Similarly, HBn (active-low) and LB (active-high) control

the high-side and low-side drives respectively for phase B. The

logical relationship between the inputs and the gate drive outputs

is defined in Table 1.

The logic sense of the inputs (active-high or active-low) are

arranged to permit the bridge to be controlled with 1, 2, or 4

inputs. The control inputs to each phase can be driven together

to control both high-side and low-side drives when synchronous

rectification is used. Driving each phase with a single input in

this way provides direction control with one input and slow

decay, synchronous rectification PWM with the other input.

Driving all four control inputs together provides fast decay with

synchronous rectification and can be used to control current in

both directions with a single PWM input.

The two phases can also operate independently providing two

half-bridge drives. In this case, the dead time, blank time, and

VDS threshold will be common to both half bridge drives.

The gate drive outputs can also be controlled through the serial

interface by setting the appropriate bit in the control register. In

the control register, all bits are active-high. The logical relation-

ship between the register bit setting and the gate drive outputs is

defined in Table 2.

The logic inputs are combined (using logical OR) with the cor-

responding bits in the serial interface control register to determine

the state of the gate drive. The logical relationship between the

combination of logic input and register bit setting and the gate

drive outputs is defined in Table 3. In most applications, either

the logic inputs or the serial control will be used. When using

only the logic inputs to control the bridge, the serial register

should be left in the reset condition with all control bits set to 0.

When using only the serial interface to control the bridge, the

inputs should be tied such that the active-low inputs are con-

nected to DL and the active high inputs connected to GND; that

is, HA and LB should be tied to GND, and HBn and LAn should

be tied to DL. The internal pull-up and pull-down resistors on

these inputs ensure that they go to the inactive state should they

become disconnected from the control signal level. However,

connecting these inputs to a fixed level can allow detection of

control input faults that would not be detected using only the

internal pull-up or pull-down.

Internal lockout logic ensures that the high-side output drive and

low-side output drive cannot be active simultaneously. When the

control inputs request active high-side and low-side at the same

time for a single phase, then both high-side and low-side gate

drives will be forced low.

Output Disable

The ENABLE input is connected directly to the gate drive output

command signal, bypassing all phase control logic. This input can

be used to provide a fast output disable (emergency cutoff) or to

provide non-synchronous fast decay PWM.

ENABLE can also be monitored by a watchdog timer by setting

the EWD bit to 1. In watchdog mode, the first change of state

on the ENABLE input will activate the gate drive outputs under

command from the corresponding phase control signals, and a

watchdog timer is started. The ENABLE input must then change

state before the end of the ENABLE timeout period (tETO). If the

ENABLE input does not change before the end of the timeout

period, then all gate drive outputs will be driven low, and the

ETO bit will be set in the Status register. Any following change

of state on the ENABLE input will reactivate the gate drive

outputs. The ETO bit remains in the Status register until cleared.

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