A3924 datasheet(32/55 Pages) ALLEGRO

32 / 55 page

Automotive, Full-Bridge MOSFET Driver

A3924

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Both high-side and low-side tests must be performed to fully

verify the connection for each phase.

Firstly, for the phase A high-side test, GHA is switched on using

the serial command register bits or the logic input terminals. A

pull-down current on phase A (ISD) is then switched on by setting

the YPH bit in the Verify Command 1 register to 1. The phase

state monitor is then used to check that the SA connection is

higher than the programmable threshold set by VPT. If the phase

state monitor output is high when YPH is reset to 0, then the

PAC bit will be set in the Verify Result 0 register, indicating the

phase A high-side is connected. The external controller is able to

determine the time required to complete the verification as the

PAC bit will only be set in the Verify Result 0 register when YPH

is reset to 0. The high-side test is then repeated for phase B, with

GHB switched on.

Secondly, for the phase A low-side test, GLA is switched on using

the serial command register bits or the logic input terminals. A

pull-up current on phase A (ISU) is then switched on by setting the

YPL bit in the Verify Command 1 register to 1. The phase state

monitor is then used to check that the SA connection is lower

than the programmable threshold set by VPT. If the phase state

monitor is low when YPL is reset to 0, then the PAC bit will be

set in the Verify Result 0 register, indicating the phase B low-side

is connected. The external controller is able to determine the time

required to complete the verification as the PAC bit will only be

set in the Verify Result 0 register when YPL is reset to 0. The

low-side test is then repeated for phase B, with GLB switched on.

Note that, during verification of the phase connections, the VDS

overvoltage detection should be masked to avoid a VDS fault

condition being detected and disabling the MOSFET under

verification.

VERIFY: VREG UNDERVOLTAGE

The VREG undervoltage detector is verified by setting the YRU

bit in the Verify Command 0 register to 1. This applies a voltage

to the comparator that is lower than the undervoltage threshold

and should cause the general fault flag to be active and a VREG

undervoltage fault bit, VRU, to be latched in the Diag 1 register.

When YRU is reset to 0, the general fault flag will be reset and

the VRU bit will remain set in the Diag 1 register until cleared. If

the VRU bit is not set, then the verification has failed.

VERIFY: VREG OVERVOLTAGE

The VREG overvoltage detector is verified by setting the YRO

bit in the Verify Command 0 register to 1. This applies a voltage

to the comparator that is higher than the overvoltage threshold

and should cause the general fault flag to be active and a VREG

overvoltage fault bit, VRO, to be latched in the Diag 1 register.

When YRO is reset to 0, the general fault flag will be reset and

the VRO bit will remain set in the Diag 1 register until cleared. If

the VRO bit is not set, then the verification has failed.

VERIFY: TEMPERATURE WARNING

The temperature warning detector is verified by setting the YTW

bit in the Verify Command 0 register to 1. This applies a voltage

to the comparator that is lower than the temperature warning

threshold and should cause the general fault flag to be active and

a temperature warning fault bit (TW) to be latched in the Status

reset and the TW bit will remain set in the Status register until

cleared. If the TW bit is not set, then the verification has failed.

VERIFY: OVERTEMPERATURE

The overtemperature detector is verified by setting the YOT bit

in the Verify Command 0 register to 1. This applies a voltage to

the comparator that is higher than the overtemperature threshold

and should cause the general fault flag to be active and an

overtemperature fault bit (OT) to be latched in the Status register.

When YOT is reset to 0, the general fault flag will be reset and

the overtemperature fault will remain in the Status register until

cleared. If the OT bit is not set, then the verification has failed.

VERIFY: V3 REGULATOR UNDERVOLTAGE

The V3 regulator undervoltage detector is verified by setting the

Y3U bit in the Verify Command 0 register to 1. This applies a

voltage to the comparator that is lower than the V3 undervoltage

threshold and should cause the general fault flag to be active

and a V3 undervoltage fault bit, V3U, to be latched in the Diag

0 register. When Y3U is reset to 0, the general fault flag will be

reset and the V3U bit will remain set in the Diag 0 register until

cleared. If the V3U bit is not set, then the verification has failed.

VERIFY: V3 REGULATOR OVERVOLTAGE

The V3 regulator overvoltage detector is verified by setting the

Y3O bit in the Verify Command 0 register to 1. This applies a

voltage to the comparator that is higher than the V3 overvoltage

threshold and should cause the general fault flag to be active

A3924 Datasheet(PDF) 32 Page - Allegro MicroSystems

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