A3924 datasheet(22/55 Pages) ALLEGRO

22 / 55 page

Automotive, Full-Bridge MOSFET Driver

A3924

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The first bit (bit 15) of the Status register contains a common

fault flag (FF), which will be high if any of the fault bits in the

Status register have been set. This allows fault condition to be

detected using the serial interface by simply taking STRn low.

As soon as STRn goes low, the first bit in the Status register (bit

15) can be read on SDO to determine if a fault has been detected

at any time since the last fault register reset. In all cases, the fault

bits in the diagnostic registers are latched and only cleared after a

fault register reset.

Note that FF (bit 15) does not provide the same function as the

general fault flag output on the DIAG terminal when STRn is

high and the DIAG output is in its default mode. The fault output

on the DIAG terminal provides an indication that either a fault is

present or the outputs have been disabled due to a latched fault

state. FF provides an indication that a fault has occurred since the

last fault reset and one or more fault bits have been set.

Chip-Level Protection

Chip-wide parameters critical for correct operation of the A3924

are monitored. These include maximum chip temperature,

minimum internal logic supply voltage, and the serial interface

transmission. These three monitors are necessary to ensure that

the A3924 is able to respond as specified.

CHIP FAULT STATE: INTERNAL LOGIC UNDERVOLTAGE

The A3924 has an independent internal logic regulator to supply

the internal logic. This is to ensure that external events, other

than loss of supply, do not prevent the A3924 from operating

correctly. The internal logic supply regulator will continue to

operate with a low supply voltage, for example if the main supply

voltage drops to a very low value during a severe cold-crank

event. In extreme low-supply circumstances, or during power-up

or power-down, an undervoltage detector ensures that the A3924

operates correctly. The logic supply undervoltage lockout cannot

be masked as it is essential to guarantee correct operation over

the full supply range.

When power is first applied to the A3924, the internal logic is

prevented from operating, and all gate drive outputs are held in

the off state until the internal regulator voltage (VDL) exceeds

the logic supply undervoltage lockout rising (turn-on) threshold,

derived from the VBB POR threshold, VBBR. At this point, all

serial registers will be reset to their power-on state, and all fault

states will be reset. The FF bit and the POR bit in the Status

taken place. The A3924 then goes into its fully operational state

and begins operating as specified.

Once the A3924 is operational, the internal logic supply continues

to be monitored. If, during the operational state, VDL drops below

logic supply undervoltage lockout falling (turn-off) threshold,

derived from VBBR, then the logical function of the A3924 cannot

be guaranteed, and the outputs will be immediately disabled. The

A3924 will enter a power-down state, and all internal activity, other

than the logic regulator voltage monitor, will be suspended. If the

logic supply undervoltage is a transient event, then the A3924 will

follow the power-up sequence above as the voltage rises.

CHIP FAULT STATE: OVERTEMPERATURE

If the chip temperature rises above the overtemperature threshold

(TJF) the general fault flag will be active and the overtemperature

bit (OT) will be set in the Status register. If ESF = 1 when an

overtemperature is detected, all gate drive outputs will be dis-

abled automatically. If ESF = 0, then no circuitry will be disabled,

and action must be taken by the user to limit the power dissipa-

tion in some way so as to prevent overtemperature damage to the

chip and unpredictable device operation. When the temperature

drops below TJF by more than the hysteresis value (TJFHys), the

fault state will be reset and when ESF = 1 the outputs re-enabled.

The general fault flag remains active until the temperature drops

below the temperature warning threshold (TJW) by more than the

hysteresis value (TJWHys). The overtemperature bit remains in the

Status register until reset.

CHIP FAULT STATE: SERIAL ERROR

If there are more than 16 rising edges on SCK, or if STRn goes

high and there are fewer than 16 rising edges on SCK, or the

parity is not odd, then the write will be cancelled without writing

data to the registers, and the SE bit will be set to indicate a data

transfer error. If the transfer is a write, then the Status register

will not be reset. If the transfer is a diagnostic or verification

result read, then the addressed register will not be reset.

Operational Monitors

Parameters related to the safe operation of the A3924 in a system

are monitored. These include parameters associated with external

active and passive components, power supplies, and interaction

with external controllers.

Voltages relating to driving the external power MOSFETs are

monitored, specifically VREG, each bootstrap capacitor voltage,

and the VGS of each gate drive output. The main supply voltage

(VBB) is only monitored for overvoltage and undervoltage events.

The logic inputs are capable of being shorted to the main supply

voltage without damage, but any high voltage on these pins will

be detected. In addition, a watchdog timer can be applied to the

ENABLE input to verify continued operation of the external

controller.

A3924 Datasheet(PDF) 22 Page - Allegro MicroSystems

A3924 Datasheet(HTML) 22 Page - Allegro MicroSystems

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