A3924 datasheet(33/55 Pages) ALLEGRO

33 / 55 page

Automotive, Full-Bridge MOSFET Driver

A3924

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

and a V3 overvoltage fault bit, V3O, to be latched in the Diag

0 register. When Y3O is reset to 0, the general fault flag will be

reset and the V3O bit will remain set in the Diag 0 register until

cleared. If the V3O bit is not set, then the verification has failed.

VERIFY: VBB SUPPLY UNDERVOLTAGE

The VBB undervoltage detector is verified by setting the YSU bit

in the Verify Command 0 register to1.This applies a voltage to

the comparator that is higher than the VBB overvoltage threshold

and should cause the general fault flag to be active and the VBB

overvoltage fault bit (VSO) to be latched in the Diag 2 register.

When YSU is reset to 0, the general fault flag will be cleared, and

the VSU bit will remain set in the Diag 2 register until cleared. If

the VSU bit is not set, then the verification has failed.

VERIFY: VBB SUPPLY OVERVOLTAGE

The VBB overvoltage detector is verified by setting the YSO bit

in the Verify Command 0 register to 1. This applies a voltage to

the comparator that is higher than the VBB overvoltage threshold

and should cause the general fault flag to be active and the VBB

overvoltage fault bit (VSO) to be latched in the Diag 2 register.

When YSO is reset to 0, the general fault flag will be reset and

the VSO bit will remain set in the Diag 2 register until cleared. If

the VSO bit is not set, then the verification has failed.

VERIFY: VGS UNDERVOLTAGE

The VGS undervoltage high-side detectors are verified by setting

the YGU bit in the Verify Command 1 register to 1 and switching

on the corresponding low-side MOSFET in sequence using the

serial command register bits or the logic input terminals. This

should cause the general fault flag to be active and the high-side

VGS undervoltage fault bit (AHU or BHU) to be latched in the

Diag 0 register. The VGS undervoltage low-side detectors are

verified by setting the YGU bit in the Verify Command 1 register

to 1 and switching on the corresponding high-side MOSFET

using the serial command register bits or the logic input termi-

nals. This should cause the low-side VGS undervoltage fault

bit to be latched in the Diag 0 register. This must be repeated

for each MOSFET to verify all VGS undervoltage comparators.

When YGU is reset to 0 or all gate drives are commanded off,

then the general fault flag will be reset, but the VGS undervoltage

fault bits will remain in the Diag 0 register until cleared. If any

VGS fault bit is not set after all MOSFETs have been switched,

then the verification has failed for the corresponding comparator.

VERIFY: BOOTSTRAP CAPACITOR UNDERVOLTAGE

FAULT

The bootstrap capacitor undervoltage detectors are verified by

setting the YBU bit in the Verify Command 0 register to 1 and

switching on a high-side MOSFET using the serial Control

general fault flag to be active and the corresponding bootstrap

undervoltage fault bit (VA or VB) to be latched in the Diag 2 reg-

ister. This must be repeated for each high-side MOSFET to verify

all bootstrap undervoltage comparators. When YBU is reset to 0

or all gate drives are commanded off, then the general fault flag

will be reset, but the bootstrap undervoltage faults will remain in

the Diag 2 register until cleared. If any bootstrap undervoltage

fault bit is not set after all MOSFETs have been switched, then

the verification has failed for the corresponding comparator.

VERIFY: MOSFET VDS OVERVOLTAGE FAULT

The VDS overvoltage high-side detectors are verified by setting

the YDO bit in the Verify Command 1 register to 1 and switching

on the corresponding low-side MOSFET using the serial Control

general fault flag to be active and the high-side VDS overvoltage

fault bit (AHO or BHO) to be latched in the Diag 1 register. The

low-side detectors are verified by setting the YDO bit in the

Verify Command 1 register to 1 and switching on the correspond-

ing high-side MOSFET using the serial command register bits

or the logic input terminals. This should cause the low-side VDS

overvoltage fault bit, ALO or BLO, to be latched in the Diag 1

VDS overvoltage comparators. When YDO is reset to 0 or all

gate drives are commanded off, then the general fault flag will be

reset, but the VDS overvoltage faults will remain in the Diag 1

after all MOSFETs have been switched, then the verification has

failed.

VERIFY: LOGIC TERMINAL OVERVOLTAGE

The logic terminal overvoltage detector is verified by setting

the YLO bit in the Verify Command 0 register to 1. This applies

a voltage to the comparator that is higher than the logic input

overvoltage threshold and should cause the logic overvoltage

fault bit (VLO) to be latched in the diagnostic register. When

YLO is reset to 0, the general fault flag will be reset, but the VLO

bit will remain set in the Status register until cleared. If the VLO

bit is not set, then the verification has failed.

A3924 Datasheet(PDF) 33 Page - Allegro MicroSystems

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