GS2962 datasheet(13/82 Pages) SEMTECH

13 / 82 page

GS2962 3G/HD/SD-SDI Serializer with Complete

SMPTE Video Support

Data Sheet

48005 - 7

October 2010

13 of 82

G7IOPROC_EN/DIS

Input

CONTROL SIGNAL INPUT.

Signal levels are LVCMOS/LVTTL compatible.

Used to enable or disable the I/O processing features.

When IOPROC_EN/DIS is HIGH, the I/O processing features of the

device are enabled. When IOPROC_EN/DIS is LOW, the I/O processing

features of the device are disabled.

Only applicable in SMPTE mode.

G8RESET

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to reset the internal operating conditions to default settings

and to reset the JTAG sequence.

Normal mode (JTAG/HOST = LOW).

When LOW, all functional blocks will be set to default conditions

and all input and output signals become high impedance.

When HIGH, normal operation of the device resumes.

JTAG test mode (JTAG/HOST = HIGH).

When LOW, all functional blocks will be set to default and the JTAG

test sequence will be reset.

When HIGH, normal operation of the JTAG test sequence resumes.

ANC_BLANK

Input

CONTROL SIGNAL INPUT.

Signal levels are LVCMOS / LVTTL compatible.

When ANC_BLANK is LOW, the Luma and Chroma input data is set

to the appropriate blanking levels during the H and V blanking

intervals.

When ANC_BLANK is HIGH, the blanking function is disabled.

Only applicable in SMPTE mode.

LOCKED

Output

STATUS SIGNAL OUTPUT.

Signal levels are LVCMOS / LVTTL compatible.

PLL lock indication.

HIGH indicates PLL is locked.

LOW indicates PLL is not locked.

JTAG/HOST

Input

CONTROL SIGNAL INPUT.

Signal levels are LVCMOS / LVTTL compatible.

Used to select JTAG test mode or host interface mode.

When JTAG/HOST is HIGH, the host interface port is configured for

JTAG test.

When JTAG/HOST is LOW, normal operation of the host interface

port resumes and the separate JTAG pins become the JTAG port.

J8TCK

Input

COMMUNICATION SIGNAL INPUT.

Signal levels are LVCMOS/LVTTL compatible.

JTAG Serial Data Clock Signal.

This pin is the JTAG clock when the JTAG/HOST pin is LOW.

Table 1-1: Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

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