TMS320VC5510 datasheet(17/86 Pages) TI

17 / 86 page

Introduction

June 2000 − Revised July 2004

SPRS076J

Table 2−2. Signal Descriptions (Continued)

SIGNAL

NAME

DESCRIPTION

OTHER‡

TYPE†

EMIF - SYNCHRONOUS BURST SRAM CONTROL SIGNALS

SSADS

O/Z

E,F

SBSRAM address strobe. SSADS is active (low) during the period of the SBSRAM access when

the address is made available to the external memory by the DSP.

SSOE

O/Z

E,F

SBSRAM output enable. SSOE is active (low) during read accesses to SBSRAM.

SSWE

SBSRAM write enable. SSWE is active (low) during write accesses to SBSRAM.

EMIF - SYNCHRONOUS DRAM CONTROL SIGNALS

SDRAS

SDRAM row address strobe. SDRAS is active (low) during the ACTV, DCAB, REFR, and MRS

commands.

SDCAS

O/Z

E,F

SDRAM address column strobe. SDCAS is active (low) during reads, writes, and the REFR and

MRS commands.

SDWE

O/Z

E,F

SDRAM write enable. SDWE is active (low) during writes, and the DCAB and MRS commands.

SDA10

SDRAM A10 address (address/autoprecharge disable). SDA10 is used during reads, writes,

and all commands.

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

CLKR0

CLKR1

CLKR2

I/O/Z

C,F,G,H

Serial shift clock reference for the receiver

DR0

DR1

DR2

Serial receive data input

FSR0

FSR1

FSR2

I/O/Z

F,G,H

Frame synchronization signal for the receiver

CLKX0

CLKX1

CLKX2

I/O/Z

C,F,G,H

Serial shift clock reference for the transmitter

DX0

DX1

DX2

O/Z

F,H

Serial transmit data output

FSX0

FSX1

FSX2

I/O/Z

F,G,H

Frame synchronization signal for the transmitter

CLKS0

CLKS1

CLKS2

External clock source to the sample rate generator

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup (always enabled)

E − Pin is high impedance in HOLD mode (due to HOLD pin).

B − Internal pulldown (always enabled)

F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).

C − Hysteresis input

G − Pin can be configured as a general-purpose input.

D − Pin has bus holder

H − PIn can be configured as a general-purpose output.

J − Internal pullup enabled by the HPE bit in the system register (SYSR)

K − Internal pulldown enabled by the HPE bit in the system register (SYSR)

TMS320VC5510 Datasheet(PDF) 17 Page - Texas Instruments

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