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TPS65010 Datasheet(PDF) 18 Page - Texas Instruments |
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TPS65010 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 50 page ![]() www.ti.com VBAT VBAT SCL SDA VBAT ISET PG AC Adapter USB port SCLK SDAT TS VINMAIN L1 VMAIN VINCORE L2 VCORE VINLDO1 VLDO1 VINLDO2 VLDO2 LOW_PWR AGND PGND INT AC USB BATT− BATT+ TEMP CHARGER/REG INTERRUPT CHARGER POWER GOOD VCORE 1.5V VMAIN 3.3V VMAIN DEFCORE GND IFLSB GND/VCC DEFMAIN VBAT BATT_COVER PB_ONOFF nPOR RESET to MPU GND VFB_LDO1 LED2 VIB GPIO1 GPIO2 GPIO3 GPIO4 VCC PS_SEQ GND HOT_RESET RESPWRON MPU_RESET PWRFAIL Battery Fail, Battery Cover Removed, Overtemp USB DP, Camera i/f Touchscreen Controller ARMIO,LCD, Keyboard, USB Host, SDIO SDRAM, FLASH i/f @ 1.8 V/2.8 V VDD, VDD1, VDD2, VDD3 VDDSHV2,8 GPIO RESPWRON MPU_RESET FIQ_PWRFAIL VDDSHV4,5 VDDSHV1,3,6,7,9 ARMIO_5/LOW_POWER OMAP1510 TPS65010 VBAT VMAIN VBAT TPS65010 SLVS149A – JUNE 2003 – REVISED JANUARY 2004 APPLICATION INFORMATION (continued) It is recommended to supply LDO1 from VMAIN as shown in Figure 25. If this is not done, then subsequent to a UVLO, OVERTEMP, or BATT_COVER = 0 condition, the RESPWRON signal goes high before the VCORE rail has ramped and stabilized. Therefore, the processor core does not receive a power on reset signal. Figure 26. Typical Application Circuit in Low Power Mode 18 |
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