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VCORE

VMAIN

VLDO1

VLDO2

95% VCORE

95% VLDO2

HOT_RESET

DEGLITCH

INT

MPU_RESET

tGLITCH

t(MPU_RESET)

SYSTEM RESET AND CONTROL SIGNALS

TPS65010

SLVS149A – JUNE 2003 – REVISED JANUARY 2004

Figure 37. State 3 to State 2 Transition (HOT_RESET Activated, See Interrupt Management Section for INT

Behavior)

The RESPWRON signal is used as a global reset for the application. It is an open drain output. The

RESPWRON signal is generated according to the Power Good comparator linked to VLDO1 and remains low for

tn(RESPWRON) sec after VLDO1 has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET and INT are

also held low.

If the output voltage of LDO1 is less than 90% of its nominal value, as RESPWRON is generated, and if the

output voltage of LDO1 is programmed to a higher value, which causes the output voltage to fall out of the 90%

window, then a RESPWRON signal is generated.

The PWRFAIL signal indicates when VCC < UVLO or when the TPS65010 junction temperature has exceeded a

reliable value or if BATT_COVER is taken low. This open drain output can be connected at a fast interrupt pin for

immediate attention by the application processor. All supplies are disabled t(uvlo), t(overtemp) or t(batt_cover) sec after

PWRFAIL has gone low, giving time for the application processor to shutdown cleanly.

BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the

TPS65010 generates a warning to the processor that the battery is likely to be removed and that it may be

prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER

pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER

has an internal 2-M

Ω pull down.

TPS65010 Datasheet(PDF) 34 Page - Texas Instruments