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TPS65010 Power States Description

TPS65010

SLVS149A – JUNE 2003 – REVISED JANUARY 2004

State 1: No Power

There are no batteries connected to the TPS65010. When main power is applied, the bandgap reference, LDOs,

and UVLO comparator start up. The RESPWRON, PWRFAIL, INT and MPU_RESET signals are held low. When

BATT_COVER goes high (de-bounced internally by the TPS65010), indicating that the battery cover has been

put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ.

RESPWRON, PWRFAIL, INT and MPU_RESET are released when the RESPWRON timer has timed out after

tn(RESPWRON) sec. If VCC remains valid and no OVERTEMP condition occurs then the TPS65010 arrives in State

2: ON. If VCC < UVLO the TPS65010 keeps the bandgap reference and UVLO comparator active such that

when VCC>UVLO (during battery charge) the supplies are automatically activated.

State 2: ON

In this state, TPS65010 is fired up and ready to go. The switching converters can have their output voltages

programmed, the LDOs can be disabled or programmed. TPS65010 can exit this state either due to an

overtemperature condition, by an undervoltage condition at VCC, by BATT_COVER going low, or by the

processor programming low power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.

State 3: Low Power Mode

This state is entered via the processor setting the ENABLE_LP bit in the serial interface and then raising the

LOW_PWR pin. The TPS65010 actually uses the rising edge of the internal signal formed by a logical AND of

the LOW_PWR and ENABLE LP signals to enter low power mode. The VMAIN switching converter remains

active, but the VCORE converter may be disabled in low power mode via the serial interface by setting the

LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by

the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1

disabled in order to minimize quiescent current) in low power mode. All TPS65010 features remain addressable

via the serial interface. TPS65010 can exit this state either due to an undervoltage condition at VCC, due to

BATT_COVER going low, due to an OVERTEMP condition, by the processor deasserting the LOW_POWER pin

or by the user activating the HOT_RESET pin or the PB_ONOFF pin.

State 4: Shutdown

This state is entered automatically when either the VCC voltage is below UVLO the threshold, or if the TPS65010

junction temperature is too high, or if the BATT_COVER pins goes low. The shutdown state is left when the error

condition no longer applies.

Table 2 indicates the typical quiescent current consumption in each power state.

Table 2. TPS65010 Typical Current Consumption

TOTAL QUIESC-

STATE

ENT

QUIESCENT CURRENT BREAKDOWN

CURRENT

30 µA-70 µA

VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference + PowerGood

30 µA-55 µA

VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference + PowerGood

13 µA

UVLO + reference circuitry

TPS65010 Datasheet(PDF) 28 Page - Texas Instruments

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