CDC5801

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH

PROGRAMMABLE DELAY AND PHASE ALIGNMENT

SCAS682A – OCTOBER 2002

6

POST OFFICE BOX 655303

–0.5 V to 4 V

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Continuous total power dissipation

see Dissipation Rating Table

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–40

°C to 85°C

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–65

°C to 150°C

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Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

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† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminals.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C‡

TA = 85°C

POWER RATING

DBQ

1400 mW

11 mW/

°C

740 mW

‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with

no air flow.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VDD (VDDP, VDDPA, VDDO)

3.0

3.3

3.6

V

High-level input voltage, VIH (CMOS)

0.7

× VDD

V

Low-level input voltage, VIL (CMOS)

0.3

× VDD

V

REFCLK low-level input voltage, VIL

0.3

× VDDREF

V

REFCLK high-level input voltage, VIH

0.7

× VDDREF

V

Input signal low voltage, VIL (STOPB, DLYCTRL, LEADLAG)

0.3

× VDDPD

V

Input signal high voltage, VIH (STOPB, DLYCTRL, LEADLAG)

0.7

× VDDPD

V

Input reference voltage for (REFCLK) (VDDREF)

1.235

VDD

V

Input reference voltage for (DLYCTRL and LEADLAG) (VDDPD)

1.235

VDD

V

High-level output current, IOH

–16

mA

Low-level output current, IOL

16

mA

Operating free-air temperature, TA

–40

85

°C

timing requirements

MIN

MAX

UNIT

Input frequency of modulation, fmod (if driven by SSC CLKIN)

33

kHz

Modulation index (nonlinear maximum 0.5%)

0.6%

Input slew rate, SR

1

4

V/ns

Input duty cycle on REFCLK

40%

60%

Input frequency on REFCLK

19

125

MHz

Allowable frequency on DLYCTRL

200

MHz

Allowable frequency on LEADLAG

400

MHz

Allowable duty cycle on DLYCTRL and LEADLAG

25%

75%