CDC5801

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH

PROGRAMMABLE DELAY AND PHASE ALIGNMENT

SCAS682A – OCTOBER 2002

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CLKOUT

20

O

Output clock

CLKOUTB

18

O

Output clock (complement)

DLYCTRL

7

I

Every rising edge on this terminal delays/advances the CLKOUT/CLKOUTB signal by 1/384th of the

CLKOUT/CLKOUTB period. (e.g., for a 90 degree delay or advancement one needs to provide 96 rising

edges). See Table 4.

GND

5

GND for VDDREF and VDDPD

GNDO

17, 21

GND for clock output terminals (CLKOUT, CLKOUTB)

GNDP

4

GND for PLL

GNDPA

8

GND for phase aligner

LEADLAG

6

I

Decides if the output clock is delayed or advanced with respect to REFCLK. See Table 4.

MULT0/DIV0

15

I

PLL multiplier and divider select

MULT1/DIV1

14

I

PLL multiplier and divider select

NC

19

Not used

PWRDNB

12

I

Active low power down state, CLKOUT/CLKOUTB goes low

P0

24

I

Mode control, see Function Table

P1

23

I

Mode control, see Function Table

P2

13

I

Mode control, see Function Table

REFCLK

2

I

Reference input clock

STOPB

11

I

Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as per Table 3

VDDPA

9

I

Supply voltage for phase aligner

VDDPD

10

I

Reference voltage for the DLYCTRL, LEADLAG terminals and STOPB function

VDDREF

1

I

Reference voltage for REFCLK

VDDO

16, 22

I

Supply voltage for the output terminals (CLKOUT, CLKOUTB)

VDDP

3

I

Supply voltage for PLL