CDC5801

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH

PROGRAMMABLE DELAY AND PHASE ALIGNMENT

SCAS682A – OCTOBER 2002

14

POST OFFICE BOX 655303

19.44 MHz

P0

P1

VDDO

GNDO

CLKOUT

NC

CLKOUTB

GNDO

VDDO

MULT0/DIV0

MULT1/DIV1

P2

VDDREF

REFCLK

VDDP

GNDP

GND

LEADLAG

DLYCTRL

GNDPA

VDDPA

VDDPD

STOPB

PWRDNB

CDC5801

Z = 50

Ω

CDCVF2310

Clock Buffer

CLK

CDCVF2310

Clock Buffer

CLK

3.3 V

3.3 V

20 R

3.3 V

Z = 50

Ω ; Length = L1

Z = 50

Ω ; Length = L1

Z = 50

Ω

3.3 V

3.3 V

3.3 V

Outputs are Phase Aligned

Between the Two Buffers

Figure 9. Using the CDC5801 Device as a Multiplier by 8 and Aligning Two Different Clocks