CDC5801 datasheet(11/16 Pages) TI

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CDC5801

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH

PROGRAMMABLE DELAY AND PHASE ALIGNMENT

SCAS682A – OCTOBER 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

state transition latency specifications

PARAMETER

FROM

TEST

CONDITIONS

MIN

TYP†

MAX

UNIT

t(powerup)

Delay time, PWRDNB

↑ to CLKOUT/

CLKOUTB output settled (excluding

t(DISTLOCK))

Powerdown

Normal

See Figure 6

t(powerup)

Delay time, PWRDNB

↑ to internal PLL and

clock are on and settled

Powerdown

Normal

See Figure 6

Delay time, power up to CLKOUT/CLKOUTB

output settled

Normal

See Figure 6

t(VDDpowerup)

Delay time, power up to internal PLL and

clock are on and settled

VDD

Normal

See Figure 6

t(MULT)

MULT0 and MULT1 change to CLKOUT/

CLKOUTB output resettled (excluding

t(DISTLOCK))

Normal

See Figure 7

t(CLKON)

STOPB

↑ to CLKOUT/CLKOUTB glitch-free

clock edges

CLK Stop

Normal

See Figure 8

t(CLKSETL)

STOPB

↑ to CLKOUT/CLKOUTB output

settled to within 50 ps of the phase before

STOPB was disabled

CLK Stop

Normal

See Figure 8

cycles

t(CLKOFF)

STOPB

↓ to CLKOUT/CLKOUTB output dis-

abled

Normal

CLK

Stop

See Figure 8

t(powerdown)

Delay time, PWRDNB

↓ to the device in the

power-down mode

Normal

Power–

down

See Figure 6

t(STOP)

Maximum time in CLKSTOP (STOPB = 0)

before reentering normal mode

(STOPB = 1)

STOPB

Normal

See Figure 8

100

µs

t(ON)

Minimum time in normal mode (STOPB = 1)

before reentering CLKSTOP (STOPB = 0)

Normal

CLK

stop

See Figure 8

100

† All typical values are at VDD = 3.3 V, TA = 25°C.

PARAMETER MEASUREMENT INFORMATION

Ω

CLKOUTB

CLKOUT

10 pF

Ω

VCM

Figure 1. Test Load and Voltage Definitions (VO(STOP), VOX, VOH, VOL)

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