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EL2157CS Datasheet(PDF) 5 Page - Intersil Corporation |
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EL2157CS Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 19 page ![]() 5 NOTES: 1. CLAMP pin and ENABLE pin specifications apply only to the EL2157. 2. All AC tests are performed on a “warmed up” part, except slew rate, which is pulse tested. 3. Standard NTSC signal = 286mVP-P, f = 3.58MHz, as VIN is swept from 0.6V to 1.314V.RL is DC coupled. 4. Disable/Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply current has reached half its final value. Closed Loop AC Electrical Specifications VS = +5V, GND = 0V, TA = 25°C, VCM = +1.5V, VOUT = +1.5V, VCLAMP = +5V, VENABLE = +5V, AV = +1, RF = 0Ω, RL = 150Ω to GND pin, unless otherwise specified. (Notes 1 and 2) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT BW -3dB Bandwidth (VOUT = 400mVP-P)VS = 5V, AV = 1, RF = 0Ω 125 MHz VS = 5V, AV = -1, RF = 500Ω 60 MHz VS = 5V, AV = 2, RF = 500Ω 60 MHz VS = 5V, AV = 10, RF = 500Ω 6MHz VS = 12V, AV = 1, RF = 0Ω 150 MHz VS = 3V, AV = 1, RF = 0Ω 100 MHz BW ±0.1dB Bandwidth (VOUT = 400mVP-P)VS = 12V, AV = 1, RF = 0Ω 25 MHz VS = 5V, AV = 1, RF = 0Ω 30 MHz VS = 3V, AV = 1, RF = 0Ω 20 MHz GBWP Gain Bandwidth Product VS = 12V, @ AV = 10 60 MHz PM Phase Margin RL = 1kΩ, CL = 6 pF 55 ° SR Slew Rate VS = 10V, RL = 150Ω, VOUT = 0V to 6V 200 275 V/µs VS = 5V, RL = 150Ω, VOUT = 0V to 3V 300 V/µs tR,tF Rise Time, Fall Time ±0.1V step 2.8 ns OS Overshoot ±0.1V step 10 % tPD Propagation Delay ±0.1V step 3.2 ns tS 0.1% Settling Time VS = ±5V, RL = 500Ω, AV = 1, VOUT = ±3V 40 ns 0.01% Settling Time VS = ±5V, RL = 500Ω, AV = 1, VOUT = ±3V 75 ns dG Differential Gain (Note 3) AV = 2, RF = 1kΩ 0.05 % dP Differential Phase (Note 3) AV = 2, RF = 1kΩ 0.05 ° eN Input Noise Voltage f = 10kHz 48 nV/ √Hz iN Input Noise Current f = 10kHz 1.25 pA/ √Hz tDIS Disable Time (Note 4) 50 ns tEN Enable Time (Note 4) 25 ns tCL Clamp Overload Recovery 7ns EL2150, EL2157 |
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