MAX5591BEUI datasheet(7/33 Pages) MAXIM

7 / 33 page

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

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TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)

(DVDD = 1.8V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Frequency

fSCLK

1.8V < DVDD < 5.25V

MHz

SCLK Pulse-Width High

tCH

(Note 7)

SCLK Pulse-Width Low

tCL

(Note 7)

CS Fall to SCLK Rise Setup Time

tCSS

SCLK Rise to CS Rise Hold Time

tCSH

0ns

SCLK Rise to CS Fall Setup

tCS0

DIN to SCLK Rise Setup Time

tDS

DIN to SCLK Rise Hold Time

tDH

5ns

SCLK Rise to DOUTDC1 Valid

Propagation Delay

tDO1

CL = 20pF, UPIO_ = DOUTDC1 mode

SCLK Fall to DOUT_ Valid

Propagation Delay

tDO2

CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB

mode

CS Rise to SCLK Rise Hold Time

tCS1

MICROWIRE and SPI modes 0 and 3

CS Pulse-Width High

tCSW

UPIO_ TIMING CHARACTERISTICS

DOUT Tri-State Time when

Exiting DOUTDC0, DOUTDC1,

and UPIO Modes

tDOZ

CL = 20pF, from end of write cycle to UPIO_

in high impedance

200

DOUTRB Tri-State Time from CS

Rise

tDRBZ

CL = 20pF, from rising edge of CS to UPIO_

in high impedance

DOUTRB Tri-State Enable Time

from 8th SCLK Rise

tZEN

CL = 20pF, from 8th rising edge of SCLK to

UPIO_ driven out of tri-state

LDAC Pulse-Width Low

tLDL

Figure 5

LDAC Effective Delay

tLDS

Figure 6

200

CLR, MID, SET Pulse-Width Low

tCMS

Figure 5

GPO Output Settling Time

tGP

Figure 6

200

GPO Output High-Impedance

Time

tGPZ

200

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