Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

GS4288C09 Datasheet(PDF) 32 Page - GSI Technology

Part # GS4288C09
Description  32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II
PDF  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  GSI [GSI Technology]
Direct Link  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS4288C09 Datasheet(HTML) 32 Page - GSI Technology

Back Button GS4288C09 Datasheet HTML 28Page - GSI Technology GS4288C09 Datasheet HTML 29Page - GSI Technology GS4288C09 Datasheet HTML 30Page - GSI Technology GS4288C09 Datasheet HTML 31Page - GSI Technology GS4288C09 Datasheet HTML 32Page - GSI Technology GS4288C09 Datasheet HTML 33Page - GSI Technology GS4288C09 Datasheet HTML 34Page - GSI Technology GS4288C09 Datasheet HTML 35Page - GSI Technology GS4288C09 Datasheet HTML 36Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 32 / 62 page
background image
288Mb Address Mapping in Multiplexed Address Mode
Data Width
Burst
Length
Ball
Address
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
x36
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
4
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
8
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
X
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
x18
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
4
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
8
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
x9
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
4
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
8
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Notes:
X = Don’t Care.
GS4288C09/18/36L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 7/2014
32/62
© 2011, GSI Technology
Configuration in Mulitplexed Mode
In Multiplexed Address mode, the Read and Write latencies are increased by one clock cycle. However, the LLDRAM II cycle time
remains the same as when in Nonmultiplexed Address mode.
Cycle Time and Read/Write Latency Configuration in Mulitplexed Mode
Parameter
Configuration
Units
12
2
3
42, 3
5
tRC
4
6
8
3
5
tCK
tRL
5
7
9
4
6
tCK
tWL
6
8
10
5
7
tCK
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
MHz
Notes:
1. tRC < 20 ns in any configuration is only available with –24 and –18 speed grades.
2. BL = 8 is not available.
3. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum
tRC is 4 cycles.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com