GS4288C09 datasheet(8/62 Pages) GSI

Part #	GS4288C09

Description	32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

PDF	62 Pages

Scroll/Zoom	100%

Manufacturer	GSI [GSI Technology]

Direct Link	http://www.gsitechnology.com

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8 / 62 page

GS4288C09/18/36L

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.03 7/2014

8/62

Power–Up Initialization Sequence

200us Min

Mode Initialization

tMRSC

Refresh

1024 Cycles NOP Cycles Min

NOP

MRS

NOP

AREF

NOP

CODE(1,2)

CODE(2)

ADDR

Bank 0

Bank 7

Valid

tDKL

tDK

tDKL

tDKH

tDK

tCKL

tCK

tCKL

tCKH

tCK

VEXT

VDD

VDDQ

VREF

VTT

Command

ADDR

All Banks(5)

Notes:

Recommend all address pins held Low during dummy MRS commands.

A10–A17 must be Low.

DLL must be reset if tCK or VDD are changed.

CK and CK must be separated at all times to prevent bogus commands from being issued.

The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any operation,

tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.

GS4288C09 Datasheet(PDF) 8 Page - GSI Technology

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