OPA2846 datasheet(19/24 Pages) TI

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OPA2846

SBOS274A −JUNE 2003 − REVISED MARCH 2004

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The total output spot noise voltage can be computed as the

square root of the squared contributing terms to the output

noise voltage. This computation adds all the contributing

noise powers at the output by superposition, then takes the

square root to get back to a spot noise voltage.

Equation 11 shows the general form for this output noise

voltage using the terms shown in Figure 12.

O +

NI ) IBNRS

) 4kTR

S NG

) I

BIRF

) 4kTR

FNG

Dividing

this

expression

the

noise

gain

(NG =1+RF/RG) will give the equivalent input-referred

spot noise voltage at the noninverting input as shown in

Equation 12.

N +

NI ) IBNRS

) 4kTR

S )

BIRF

)

4kTR

Inserting high resistor values into Equation 12 can quickly

dominate the total equivalent input referred noise. A 105

Ω

source impedance on the noninverting input will add a

thermal voltage noise term equal to that of the amplifier

itself. As a simplifying constraint, set RG = RS in

Equation 12 and assume an RS/2 source impedance at

the noninverting input (where RS is the signal’s source

impedance with another matching RS to ground on the

noninverting input). This results in Equation 13, where

NG > 10 has been assumed to further simplify the

expression.

NI)

2 ) 5

BRS

2 ) 4kT

Evaluating this expression for RS = 50Ω will give a total

equivalent input noise of 1.64nV/

√Hz. Note that the NG

has dropped out of this expression. This is valid only for

NG > 10.

FREQUENCY RESPONSE CONTROL

Voltage-feedback op amps exhibit decreasing closed-loop

bandwidth as the signal gain is increased. In theory, this

relationship is described by the GBP shown in the

specifications. Ideally, dividing GBP by the noninverting

signal gain will predict the closed-loop bandwidth. In

practice, this only holds true when the phase margin

approaches 90

°, as it does in high gain configurations. At

low gains (with an increased feedback factor), most

high-speed amplifiers will exhibit a more complex

response with lower phase margin. The OPA2846 is

compensated

give

maximally-flat,

2nd-order,

Butterworth, closed-loop response at a noninverting gain

of +10 (see Figure 1). This results in a typical gain of +10

bandwidth of 300MHz, far exceeding that predicted by

dividing the 1650MHz GBP by 10. Increasing the gain will

cause the phase margin to approach 90

° and the

bandwidth to more closely approach the predicted value of

(GBP/NG). At a gain of +40, the OPA2846 will show the

41MHz bandwidth predicted using the simple formula and

the typical GBP of 1650MHz.

Inverting operation offers some interesting opportunities to

increase the available GBP. When the source impedance

is matched by the gain resistor (see Figure 2), the signal

gain is (1 + RF/RG) while the noise gain for bandwidth

purposes is (1 + RF/2RG). This cuts the noise gain almost

in half, increasing the minimum stable gain for inverting

operation under these condition to −12 and the equivalent

GBP to 3.2GHz.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load

conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an A/D converter, including

additional external capacitance which may be recom-

mended to improve ADC linearity. A high-speed, high

open-loop gain amplifier like the OPA2846 can be very

susceptible to decreased stability and closed-loop re-

sponse peaking when a capacitive load is placed directly

on the output pin. When the amplifier’s open-loop output

resistance is considered, this capacitive load introduces

an additional pole in the signal path that can decrease the

phase margin. Several external solutions to this problem

have been suggested. When the primary considerations

are frequency response flatness, pulse response fidelity,

and/or distortion, the simplest and most effective solution

is to isolate the capacitive load from the feedback loop by

inserting a series isolation resistor between the amplifier

output and the capacitive load. This does not eliminate the

pole from the loop response, but rather shifts it and adds

a zero at a higher frequency. The additional zero acts to

cancel the phase lag from the capacitive load pole, thus

increasing the phase margin and improving stability.

The Typical Characteristics show the recommended RS vs

Capacitive Load and the resulting frequency response at

the load. Parasitic capacitive loads greater than 2pF can

begin to degrade the performance of the OPA2846. Long

PC board traces, unmatched cables, and connections to

multiple devices can easily cause this value to be

exceeded. Always consider this effect carefully, and add

the recommended series resistor as close as possible to

the OPA2846 output pin (see the Board Layout section).

The criterion for setting this RS resistor is a maximum

bandwidth, flat frequency response at the load. For the

OPA2846 operating in a gain of +10, the frequency

response at the output pin is very flat to begin with,

allowing relatively small values of RS to be used for low

capacitive loads. As the signal gain is increased, the

unloaded phase margin will also increase. Driving

capacitive loads at higher gains will require lower RS

values than those shown for a gain of +10.

(11)

(12)

(13)

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