PCM1730

SLES021 – NOVEMBER 2001

7

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system clock and reset functions (continued)

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

SAMPLING FREQUENCY

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

32 kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1 kHz

5.6488

8.4672

11.2896

16.9344

22.5792

33.8688

48 kHz

6.144

9.216

12.288

18.432

24.576

36.864

96 kHz

12.288

18.432

24.576

36.864

49.152

73.728

192 kHz

24.576

36.864

49.152

73.728

See Note 4

See Note 4

NOTE 4: This system clock rate is not supported for the given sampling frequency.

power-on and external reset functions

The PCM1730 includes a power-on reset function. Figure 2 shows the operation of this function. The system

(pin 1). This allows an external controller or master reset circuit to force the PCM1730 to initialize to its reset

state. Figure 3 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of

20 ns. The RST pin is then set to a logic 1 state, which starts the initialization sequence, which requires 1024

system clock periods. The external reset is especially useful in applications where there is a delay between

PCM1730 power up and system clock activation. In this case, the RST pin should be held at a logic 0 level until

the system clock has been activated. The RST pin may then be set to logic 1 state to start the initialization

sequence.