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Integrated Functions (Continued)

4.5.8

Graphics Memory Map

The GXm processor supports a maximum of 4 MB of

graphics memory and will map it to an address space (see

Figure 4-2 on page 93) higher than the maximum amount

of installed RAM. The graphics memory aperture physi-

cally resides at the top of the installed system RAM. The

start address and size of the graphics memory aperture

are programmable on 128 KB boundaries. Typically, the

system BIOS sets the size and start address of the graph-

ics memory aperture during the boot process based on

the amount of installed RAM, user defined CMOS set-

tings, and display resolution. The graphics pipeline and

display controller address the graphics memory with a 20-

bit offset (address bits [21:2]) and four byte enables into

the graphics memory aperture. The graphics memory

stores several buffers that are used to generate the dis-

play: the frame buffer, compressed display buffer, VGA

memory, and cursor pattern(s). Any remaining off-screen

memory within the graphics aperture may be used by the

display driver as desired or not at all.

4.5.8.1

DC Memory Organization Registers

The display controller contains a number of registers that

allow full programmability of the graphics memory organi-

zation. This includes starting offsets for each of the buffer

regions described above, line delta parameters for the

frame buffer and compression buffer, as well as com-

pressed line-buffer size information. The starting offsets

for the various buffers are programmable for a high

degree of flexibility in memory organization.

4.5.8.2

Frame Buffer and Compression Buffer

Organization

The GXm processor supports primary display modes

640x480, 800x600, and 1024x768 at both 8 BPP and 16

BPP, and 1280x1024 at 8 BPP. Pixels will be packed into

DWORDs as shown in Figure 4-15.

In order to simplify address calculations by the rendering

hardware, the frame buffer is organized in an XY fashion

where the offset is simply a concatenation of the X and Y

pixel addresses. All 8 BPP display modes with the excep-

tion of 1280x1024 resolution will use a 1024-byte line

delta between the starting offsets of adjacent lines. All 16

BPP display modes and 1280x1024x8 BPP display

modes will use a 2048-byte line delta between the starting

offsets of adjacent lines. If there is room, the space

between theend of alineand thestart of thenextlinewill

be filled with the compressed display data for that line,

thus allowing efficient memory utilization. For 1024x768

display modes, the frame-buffer line size is the same as

the line delta, so no room is left for the compressed dis-

play data between lines. In this case, the compressed dis-

play buffer begins at the end of the frame buffer region

and is linearly mapped.

Figure 4-15. Pixel Arrangement Within a DWORD

Bit Position

3130 292827 2625 24 2322 2120 1918 171615 1413 12 1110 9

8 7

6 5

4 3 2

1 0

Address

Pixel Org - 8 BPP

(3,0)

(2,0)

(1,0)

(0,0)

Pixel Org - 16 BPP

(1,0)

(0,0)

(1023,0)

(1023, 1023)

(0, 0)

(0, 1023)

DWORD 0

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