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Revision 3.1

Integrated Functions (Continued)

4.5.8.3

VGA Display Support

The graphics pipeline contains full hardware support for

theVGA frontend.The VGAdataisstoredina256 KB

buffer located in graphics memory. The main task for Soft-

VGA is converting the data in the VGA buffer to an 8 BPP

frame buffer that can be displayed by the GXm proces-

sor’s hardware.

For some modes, the display controller can display the

VGA data directly and the data conversion is not neces-

sary. This includes standard VGA mode 13h and the vari-

ations of that mode used in several games; the display

controller can also directly display VGA planar graphics

modes D, E, F, 10, 11, and 12. Likewise, the hardware can

directly display all of the higher-resolution VESA modes.

Since the frame buffer data is written directly to memory

instead of travelling across an external bus, the GXm pro-

cessor outperforms typical VGA cards for these modes.

The display controller, however, does not directly support

text modes. SoftVGA must then convert the characters

and attributes in the VGA buffer to an 8 BPP frame buffer

the hardware uses for display refresh. See Section 4 “Vir-

tual Subsystem Architecture” for SoftVGA details.

4.5.8.4

Cursor Pattern Memory Organization

The cursor overlay patterns are loaded to independent

memory locations, usually mapped above the frame buffer

and compressed display buffer (off-screen). The cursor

buffer must start on a 16-byte aligned boundary. It is lin-

early mapped, and is always 256 bytes in size. If there is

enough room (256 bytes) after the compression-buffer line

but before the next frame-buffer line starts, the cursor pat-

tern may be loaded into this area to make efficient use of

the graphics memory.

Each pattern is a 32x32-pixel array of 2-bit codes. The

codes are a combination of AND mask and XOR mask for

a particular pixel. Each line of an overlay pattern is stored

as two DWORDs, with each DWORD containing the AND

masks for 16 pixels in the upper word and the XOR masks

for 16 pixels in the lower word. DWORDs are arranged

with the leftmost pixel block being least significant and the

rightmost pixel block being most significant. Pixels within

words are arranged with the leftmost pixels being most

significant and the rightmost pixels being least significant.

Multiple cursor patterns may be loaded into the off-screen

memory. An application may simply change the cursor

start offset to select a new cursor pattern. The new cursor

pattern will be used at the start of the next frame scan.

4.5.9

Display Controller Registers

The Display Controller maps 100h locations starting at

GX_BASE+8300h. Refer to Section 4.1.2 “Control Regis-

ters” on page 94 for instructions on accessing these regis-

ters.

The Display Controller Registers are divided into six cate-

gories:

• Configuration and Status Registers

• Memory Organization Registers

• Timing Registers

• Cursor and Line Compare Registers

• Color Registers

• Palette and RAM Diagnostic Registers

Table 4-29 summarizes these registers and locations and

the following subsections give detailed register/bit for-

mats.

Table 4-29. Display Controller Register Summary

GX_BASE+

Memory Offset

Type

Name/Function

Default

Value

Configuration and Status Registers

8300h-8303h

R/W

DC_UNLOCK

Display Controller Unlock — This register is provided to lock the most critical memory-

mapped display controller registers to prevent unwanted modification (write operations).

Read operations are always allowed.

00000000h

8304h-8307h

R/W

DC_GENERAL_CFG

Display Controller General Configuration — General control bits for the display controller.

00000000h

8308h-830Bh

R/W

DC_TIMING_CFG

Display Controller Timing Configuration — Status and control bits for various display

timing functions.

xx000000h

830Ch-830Fh

R/W

DC_OUTPUT_CFG

Display Controller Output Configuration — Status and control bits for pixel output

formatting functions.

xx000000h

Memory Organization Registers

8310h-8313h

R/W

DC_FB_ST_OFFSET

Display Controller Frame Buffer Start Address — Specifies offset at which the frame buffer

starts.

xxxxxxxxh

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