GXM datasheet(139/244 Pages) NSC

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Integrated Functions (Continued)

4.5.9.1

Configuration and Status Registers

The Configuration and Status Registers group consists of

four 32-bit registers located at GX_BASE+8300h-830Ch.

These registers are described below and Table 4-30 gives

their bit formats.

• Display Controller Unlock (DC_UNLOCK)

- This register is provided to lock the most critical

memory-mapped display controller registers to

prevent unwanted modification (write operations).

Read operations are always allowed.

• Display Controller General Configuration

(DC_GENERAL_CFG)

- General control bits for the display controller.

• Display Controller Timing Configuration

(DC_TIMING_CFG)

- Status and control bits for various display timing

functions.

• Display Controller Output Configuration

(DC_OUTPUT_CFG)

- Status and control bits for pixel output formatting

functions.

Table 4-30. Display Controller Configuration and Status Registers

Bit

Name

Description

GX_BASE+8300h-8303h

DC_UNLOCK Register (R/W)

Default Value = 00000000h

31:16

RSVD

Reserved: Set to 0.

15:0

UNLOCK_

CODE

Unlock Code: This register must be written with the value 4758h in order to write to the protected regis-

ters. The following registers are protected by the locking mechanism.

DC_GENERAL_CFG

DC_CB_ST_OFFSET,

DC_BUF_SIZE,

DC_V_TIMING_2

DC_TIMING_CFG,

DC_CURS_ST_OFFSET,

DC_H_TIMING_1,

DC_V_TIMING_3

DC_OUTPUT_CFG,

DC_H_TIMNG_2,

DC_FP_H_TIMING

DC_FB_ST_OFFSET,

DC_LINE_DELTA,

DC_FP_V_TIMING

GX_BASE+8304h-8307h

DC_GENERAL_CFG (R/W)

Default Value = 00000000h

DDCK

Divide Dot Clock: Divide internal DOTCLK by two relative to PCLK (pertains only to 16 BPP display

modes utilizing an eight-bit RAMDAC): 0 = Disable; 1 = Enable.

DPCK

Divide Pixel Clock: Divide PCLK by two relative to internal DOTCLK (pertains only to display modes that

pack two pixels together such as 1280x1024 on an external CRT only): 0 = Disable; 1 = Enable.

VRDY

Video Ready Protocol: 0 = Low speed video port, use with V2.3 and older.

1 = High speed video port, use with V2.4 and newer.

VIDE

Video Enable: Motion video port: 0 = Disable; 1 = Enable.

SSLC

Split-screen Line Compare: VGA line compare function: 0 = Disable; 1 = Enable.

When enabled, the internal line counter will be compared to the value programmed in the DC_SS

_LINE_CMP register. If it matches, the frame buffer address will be reset to zero. This enables a split

screen function.

CH4S

Chain 4 Skip: Allow display controller to read every 4th DWORD from the frame buffer for compatibility

with the VGA: 0 = Disable; 1 = Enable.

DIAG

FIFO Diagnostic Mode: This bit allows testability of the on-chip Display FIFO and Compressed Line

Buffer via the diagnostic access registers. A low-to-high transition will reset the Display FIFO’s R/W point-

ers and the Compressed Line Buffer’s read pointer. 0 = Normal operation; 1 = Enable.

LDBL

Line Double: Allow line doubling for emulated VGA modes: 0 = Disable; 1 = Enable.

If enabled, this will cause each odd line to be replicated from the previous line as the data is sent to the dis-

play. Timing parameters should be programmed as if no pixel doubling is used, however, the frame buffer

should be loaded with half the normal number of lines.

CKWR

Clock Write: This bit will be output directly to an external clock chip or SYNDAC. The bit should be pulsed

high and low by the software to strobe data into the chip.

Note that this bit can be used in conjunction with the DACRS[2:0] pins.

22:20

DAC_RS[2:0]

RAMDAC Register Selects: This 3-bit field sets the register select inputs to the external RAMDAC for the

next cycle. It is used to allow access to the extended register set of the RAMDAC. Alternatively, these bits

may be used in selecting the frequency for an external clock chip or SYNDAC. If more than eight frequency

selections are required, the RAMDAC extended register programming sequence must be used or the addi-

tional select bit must be provided by some other means.

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