GXM datasheet(143/244 Pages) NSC

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Integrated Functions (Continued)

PDEL

Panel Data Enable Low:

0 = This bit will cause the PANEL[8:0] data bus to be driven to a logic low level to effectively blank an

attached flat panel display or disable the lower panel data bus if it is not required.

1= If no flat panel is attached, the PANEL[8:0] data bus will be driven with active pixel data. If a flat panel is

attached, setting this bit high will have no effect

− the lower panel bus will be driven based upon the power

sequencing logic.

PRMP

Palette Re-map:

0 = The modified codes are sent to the RAMDAC and the external palette should uses the modified map-

ping.

1 = Bits [8:1] of the palette output register are routed to the RAMDAC data bus. The GXm processor inter-

nal palette RAM may be loaded with 8-bit VGA indices to translate the modified codes stored in display

memory so that the RAMDAC data bus will contain the expected indices. The modified codes are used to

achieve character blinking in VGA text modes. This mode should be set high set high only for desktop sys-

tems with no flat panel attached. It should only be necessary when 8514/A or VESA standard feature con-

nector support is required.

CKSL

Clock Select: Selects output used to clock PANEL[17:0], FPHSYNC, FPVSYNC, and ENADISP output

pins.

1= PCLK

0 = FPCLK (based upon the power sequencing logic)

This bit should be high when using a 16-bit RAMDAC.

9FRMS

Frame Rate Modulation Select:

0 = Enables FRM circuitry to change the pattern displayed every frame.

1 = Enables FRM circuitry to change the pattern displayed every two frames (to allow for slower response

time liquid crystal materials).

83/4ADD

3- or 4-bit Add:

0 = Enables dither and FRM circuitry to operate on the 3 most significant bits of each color component for

9-bit TFT panels.

1 = Enables the dither and FRM circuitry to operate on the 4 most significant bits of each color component

for 12-bit TFT panels.

7RSVD

Reserved: Must be set to 0.

6RSVD

Reserved: Must be set to 0.

5RSVD

Reserved: Must be set to 0.

4DITE

Dither Enable: Allow a 2x2 spatial dither on the 3-bit or 4-bit color value. Note that dither will not be sup-

ported for 12-bit TFT panels when FRM is enabled. 0 = Disable; 1 = Enable.

3FRME

Frame-Rate Modulation Enable: Allow FRM to be performed on the 3-bit or 4-bit color value using the

next most significant bit after the least significant bit sent to the panel.

0 = Disable (no FRM performed);

1 = Enable.

2PCKE

PCLK Enable:

0 = PCLK is disabled and a low logic level is driven off-chip. Also, the RAMDAC data bus is driven low.

1 = Enable PCLK to be driven off-chip.

This clock operates the RAMDAC interface.

16FMT

16 BPP Format: Selects RGB display mode:

0 = RGB 5-6-5 mode

1 = RGB 5-5-5 display mode

This bit is only significant if 8 BPP is low, indicating 16 BPP mode.

08BPP

8BPP / 16BPP Select:

0 = 16-bit per pixel display mode is selected. (Bit 1 of OUTPUT_CONFIG will indicate the format of the 16

bit data.)

1 = 8-bit-per-pixel display mode is selected. This is the also the mode used in VGA emulation.

Table 4-30. Display Controller Configuration and Status Registers (Continued)

Bit

Name

Description

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